eGaN(tm)-Silicon Power Shoot-Out: Part 1 Comparing Figure of Merit (FOM)

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One yardstick to compare enhancement mode GaN (eGaN) power devices with state-of-the-art silicon MOSFETs is FOM. However, beyond these pure mathematical numbers, there are other device and package related parameters that significantly influence in-circuit performance. To compare devices we will restrict ourselves to commercially available eGaN devices. We shall also limit the MOSFET's voltage range to between 40 and 200V as to make direct comparisons without extrapolation.

FOM is useful because no matter what the die size is, the FOM is almost constant for a given technology or device generation (under certain assumptions). To understand the derivation of FOM, we have to look at the GaN's parasitic reactances, as shown in Fig. 1. In addition, we must identify the GaN's parameters, which are listed in Table 1. Now we can look at the two distinct FOMs:

Switching FOM (lower is better): For measuring switching performance (R_DS(ON)x Q_GD) is used as Q_GD plays a dominant role in switching loss, and it is impossible to reduce this number without increasing R_DS(ON) for a given technology. This is considered a good measure of switching performance, although the use of Q_SW (Q_GD + Q_GS2) instead of Q_GD would be better, but these values are not always given in datasheets.
Rectifier FOM (lower is better): This is the traditional MOSFET FOM, and determines rectifier performance in terms of conduction and gate drive power loss (R_DS(ON)x Q_G). For a “soft” switching device, where Q_GD is not important, you would like to lower R_DS(ON) to improve efficiency, but this increases Q_G and thereby increases gate drive losses and overdrive time. It would be better to include Q_OSS and Q_RR together with Q_G for evaluating performance, but while R_DS(ON) and Q_G have reasonable standard conditions, Q_RR has no standard, and is frequently specified at unrealistic di/dt and current levels. Variation with conditions is also absent from datasheets. Q_OSS is also omitted in many cases or sometimes combined with Q_RR. Its conditions also do not have a standard (eGaN transistors have no measurable Q_RR, and low Q_OSS per-unit-area when compared with silicon MOSFETs, but have been omitted from this analysis).

Of these two FOMs, the switching performance is more important in “hard switching” converter circuits. Fig. 2 plots R_DS(ON) vs. Q_GD for eGaN power transistors as well as for different equivalent silicon MOSFETs. We can see that, based on switching FOM, the eGaN transistors offer a distinct advantage over any equivalent voltage rated silicon device, as shown in some general observations:

The 40V eGaN transistors are comparable to the current state of the art 25V lateral silicon devices.
For comparison, some original 100V devices from around the start of theMOSFET revolution (circa~1980) are also included. These show that during the past 30 years of MOSFET improvement, the switching FOM has gone down by a factor of 40! However, as silicon is starting to approach its theoretical limits it seems unlikely that the next 30 years will see a further 40X improvement.
In contrast though, it does seem likely that eGaN transistors will have a 40 times mprovement in an even smaller amount of time. With 200V devices already having similar FOMs as the best 100V silicon available today, this is a very exciting prospect indeed!

The rectifier FOM is shown in Fig. 3 R_DS(ON)vs. Q_G for the eGaN power transistors as well as for different equivalent silicon MOSFETs. From this we can draw a number of conclusions:

Although the improvement in conduction FOM is not nearly as dramatic as for switching FOM, it still delivered a 20X improvement over the last 30 years. This lower increase in performance can be explained by considering that the development of technologies to improve the more critical switching performance (such as trench) has caused a relative rise in input capacitance, which adversely affects the rectifier FOM.
eGaN power transistors show an even stronger improvement over equivalent silicon devices.
Zero Q_RR and lower Q_OSS significantly favor eGaN transistors as well, but have been omitted in this comparison as they are poorly characterized in silicon.

Although FOM is a useful tool for comparing switching power devices, there are a number of other parameters of equal importance that also need to be considered. To discuss each of these in detail, they will be divided into two sections:

Device / Die related parameters
Package related issues

DEVICE RELATED PARAMETERS

With synchronous rectification much of the traditional diode conduction losses have been eliminated, but there is a price to be paid for doing this. Since the MOSFET must turn off before voltage commutation, the body diode must also conduct current for a small period of time. This in itself is not that significant, but the MOSFET body diode typically has very poor reverse recovery characteristics (high Q_RR) that must now be recovered once it has conducted current. Attempts to commutate the current to an external Schottky, or other high performance diode, has been limited by the lack of commutation voltage (body diode forward drop), and the large loop inductance between the devices that limits the di/dt, and therefore lengthens the commutation time. This can be partially overcome through cellular integration of the Schottky or deliberate improvement of the MOSFETís parasitic body diode. The actual extent of the Q_RR losses is difficult to predict and compare as datasheet test conditions vary widely between parts and manufacturers. Some example conditions and results are shown in Table 2. Note that higher initial current should result in a much larger Q_RR and reverse recovery time (t_RR) values.

As seen in Fig. 4 , EPCís eGaN transistor structure is a lateral device, absent of the parasitic bipolar junction common to silicon MOSFETs. As such, body diode operation has a different mechanism, but similar function. With zero bias from gate to source, there is an absence of electrons under the gate region (device is off). As the drain voltage is decreased, a positive bias on the gate is created relative to the drift region, injecting electrons under the gate. Once the gate threshold is reached, there will be sufficient electrons under the gate to form a conductive channel. The benefit of this mechanism is that there are no minority carriers involved in conduction, and therefore no reverse recovery losses. As it takes a threshold voltage to turn on an eGaN transistor in the reverse direction, the forward voltage of the ëbody diodeí is higher than silicon transistors (about 1.8V for a typical eGaN device¹). As with silicon MOSFETs, care should be taken to minimize body diode conduction.

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OUTPUT CAPACITANCE LOSSES

During “hard” switching (device turning on with full bias voltage across drain-source) of a half-bridge, energy equal to that stored in the COSS of both devices is dissipated. In a typical buck converter, one of the switching edges is “soft” switching (device turn-on with no voltage across drain-source while its own body diode is conducting prior to turn-on). In the past, this loss component was negligible compared to the actual switching loss, but, as device switching FOM keeps improving, this component is becoming more important. In fact, a few manufacturers (including EPC) are starting to add typical QOSS numbers to their datasheets. Alternatively this can be estimated by integrating the COSS vs. voltage curve.

In Fig. 5, the COSS vs. voltage for 100 V and 200 V eGaN transistor and silicon MOSFETs is compared. (All devices have been normalized to 25 mΩ). Since the area under the curve is important, both the initial (near zero bias) value and the final high bias value affect the total QOSS. Due to the inherently smaller lateral structure, eGaN devices have much lower initial COSS values. At high bias, however, COSS does not drop away as quickly as with silicon. Overall, the total QOSS losses are much lower than comparable silicon as evident when plotting QOSS vs. voltage for the same devices as in Fig. 6. At half rated voltage, the eGaN parts show between two thirds and half the QOSS losses of comparative silicon devices.

PARAMETER TEMPERATURE DEPENDENCE

One of the main advantages of eGaN over silicon is the lower increase in on-resistance (RDS(ON)) with temperature, as shown in Fig. 7. Whereas silicon has >70% increase in RDS(ON) between 25°C and 100°C, eGaN shows a 40% increase. This translates into more than 20% lower RDS(ON) at a typical 100°C die temperature assuming the same initial RDS(on) at 25°C.

It is well known that, unlike minority carrier devices, silicon MOSFETs have a positive RDS(ON) temperature coefficient, making them ideal for paralleling with no thermal run-away. What is less known is that, due to the negative temperature coefficient on the voltage threshold, this does not translate into dynamic current sharing. This can also be an issue for linear amplifiers or similar applications where the MOSFETs are normally run in saturation. For a typical 200V MOSFET, this temperature coefficient is 0.325%/°C. eGaN devices also have a negative temperature coefficient to the voltage threshold, but it is less than 300ppm/°C and will therefore dynamically share for all but the smallest of drain currents.

As low-voltage silicon MOSFET performance has improved over the last number of years, the need for high performance packaging has become a major limiting factor in overall device performance. This has lead to the development of such innovative packages as the DirectFET2, or PolarPak3. But, what exactly are the requirements of a high performance package?

In general, semiconductor devices are packaged to improve robustness and ease of handling. In addition, at higher voltages some package forms are required to meet voltage clearance and creepage requirements that might not be possible without some form of encapsulation. In doing so, however, the packaged device's characteristics are degraded compared to the bare semiconductor die. This performance degradation comes in the form of increased cost, increased on-resistance, increased lead inductance and reduced thermal performance.

What sets high performance packaging apart is being able to realize the required advantages of device packaging while minimizing the drawbacks: in other words less is more. With low voltage, leadless dual-side-cooled packaging such as DirectFET, PolarPak or flip-chip becomes an elegant solution. Here the choice of package is largely dictated by the device terminal structure; vertical vs. lateral. A lateral device lends itself to easy flip-chip packaging (e. g. Greatwall BGA MOSFETs4), while a vertical, “flipped” device needs to bring the “back” terminal down to the printed circuit board (such as DirectFET or PolarPak). In a similar fashion, eGaN devices are flip-chip packages with bar grid arrays rather than ball grids where the interdigitation of source and drain terminals is used to minimize both on-resistance and parasitic inductance.

PACKAGE RESISTANCE, INDUCTANCE

In Fig. 8 the estimated packaging resistance of different standard power packages is shown alongside the eGaN flip-chip parts.

The addition of package inductance can have varied effects, depending on which terminal of the die the package inductance is added. Overall package inductance comparison are shown in Fig. 9 for the eGaN flip-chip die compared to estimated values for some standard power packages. Common source inductance (inductance inside the package connected to the source terminal that carry both drain and gate return currents) can significantly increase switching losses by slowing down device switching through induced opposition of the applied gate voltage.

Consider the turn-on of a device, as shown in Fig. 10. In simple terms, as it reaches threshold voltage and starts to carry increasing current, this dI/dt induces a voltage across the source inductance that opposes the gate drive voltage, trying to turn the device back off. The same is true during turn-off where the induced voltage adds to the gate drive voltage, thus trying to keep the device on. It is therefore critical to minimize common source impedance for optimum switching performance.

The need to minimize both package resistance and common source inductance are well known to silicon device manufactures and has lead to inventions such as the ribbon bonds, copper clip/strap5, etc to reduce package resistance and adding separate driver source pins such as IXYS DE-Series6 and ThinPak7 that reduces common source inductance or PolarPAk8, DirectFet9 which reduces both.

As end products face the pressures of lower cost and smaller size, the size of the power devices has become of increasing importance. In general, a smaller size is desirable as long as the thermal requirements can be met. The act of encapsulating a device inside a package will alMost always deteriorate thermal and electrical performance. eGaN devices allow a much lower on-resistance per unit area for the same voltage rating, which in turn reduces die and package size. Table 3 compares eGaN devices to the smallest packaged silicon device with similar RDS(ON) specifications.

Apart from an improved Figure of Merit, today's eGaN devices other advantages over silicon. Most notable is the lack of diode reverse recovery losses (QRR), which is significant at higher voltage. Other advantages are lower QOSS and better RDS(ON) vs. temperature. On the balance side, the losses from the higher eGaN “body diode” forward drop — important at lower voltages only - need to be minimized through the proper timing of the gating signals.

The eGaN device's lateral structure also lends itself to flip-chip packaging, which is a very high performance packaging solution due to the minimal increase in on-resistance and terminal inductance. Add to this a distinct die area advantage over silicon, and the resultant solution is a superior power device in a high performance package that is significantly smaller than anything available today.

FUTURE DEVELOPMENTS

In a future issue, we will discuss the requirements on getting the most out of these eGaN devices. This will cover both the electrical aspects such as gate driver requirements and proper device rating; and mechanical requirements including device footprint, proper layout, assembly and thermal requirements.