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ONE OF TI'S introductions is the 6 A TPS84620 that uses innovative lead frame packaging to achieve 800 W/in.3 power density with up to 95 % efficiency. Thermal impedance is 13°C/W junction-to-ambient, which is a 30% improvement over previous generations. The device delivers its full 6 A rated output over a -40°C to 85°C ambient temperature without external airflow.
As shown in Fig. 1, the TPS84620 is a synchronous buck converter integrating an inductor and passive components. It requires only three external components: input and output capacitors and a resistor (RSET) that sets the output voltage. The entire circuit fits into a low profile, 9×15×2.8 mm BQFN package with less than a 200 mm2 footprint.
The TPS84620 operates from a 4.5V to 14.5V input. Output adjustment range is from 1.2V to 5.5V using the external RSET resistor. An optional split power rail allows inputs down to 1.7V. Its adjustable switching frequency range is 480 kHz to 780 kHz, synchronizable to an external clock.
Various applications are possible for the converter by using the VIN and PVIN pins together or separately. VIN supplies the internal control circuits. PVIN provides the input voltage to the power converter system. With both pins tied together, the input voltage can range from 4.5V to 14.5V. Using the VIN separately from PVIN, the VIN pin must be between 4.5V and 14.5V, and the PVIN pin can range from 1.7V to 14.5V.
An internal UVLO (undervoltage lockout) circuit disables the device if VIN falls below its 4.5V (max) threshold and 150 mV (typical) hysteresis. If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, you can program the UVLO pin for the new value.
During power up of the converter, internal soft-start circuitry limits in-rush current drawn from the input source. The converter's soft-start circuitry introduces a short time delay from the point that it recognizes a valid input voltage.
The PWRGD pin is an open drain output. Once the voltage on VSENSE+ is between 94% and 106% of the set voltage, it releases the PWRGD pin pull-down and the pin floats. In operation, use a PWRGD pull-up resistor of 10 kΩ to 100 kΩ connected to 5.5 V or less.
VSENSE+ must be connected to VOUT at the load, or at the device pins. This improves load regulation by allowing the device to compensate for any I×R voltage drop between its output pins and the load. The high output current flowing through the pin and copper trace resistance can cause and I×R drop that should be limited to 300 mV (max.).
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Cycle-by-cycle current limiting protects the TPS84620 against overcurrent load faults, during which the output voltage is reduced. Removing the overcurrent condition returns the output voltage to its set value.
Internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C (typical). The device reinitiates the power up sequence when the junction temperature drops below 165°C (typical).
High-quality, computer-grade electrolytic capacitors are recommended. Aluminum electrolytics provide adequate decoupling over the 2 kHz to 150 kHz operational range, and are suitable when ambient temperatures are above 0°C. However, aluminum electrolytic performance is less effective above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output.
The associated input capacitor should be a 100µF ceramic and/or polymer-tantalum type. Conventional tantalum capacitors may not have a stated ESR or surge current rating, so they are not recommended for use with the TPS84620.
If the ambient operating temperature is less than 0°C use polymer-electrolytic capacitors, such as Sanyo OS-CON types that have low ESR, high rated surge and power dissipation, ripple current filtering capability, and small package size.
Required output capacitance value depends on the selected output voltage. The output capacitance can be made up of either all ceramic capacitors, or a combination of ceramic and bulk capacitors. The amount of required output capacitance must include at least one 47 µF ceramic capacitor.
Optimal electrical and thermal performance, requires an optimized PCB layout. Among these considerations are:
- Minimize conduction loss and thermal stress by using large copper areas for power planes (VIN, VOUT, and PGND).
- Minimize high frequency noise by placing ceramic input and output capacitors close to the module pins.
- Locate additional output capacitors between the ceramic capacitor and the load.
- Place a dedicated AGND copper area beneath the TPS84620.
- Isolate the PH pin copper area from the VOUT copper area using the AGND copper area.
- Connect the AGND and PGND copper area at one point; near the output capacitors.
- Place RSET as close as possible to the VADJ pin.
- Use multiple vias to connect the power planes to internal layers.
TI's other recent power supply introduction, the TPS82671, also employs space-saving packaging techniques. It is the industry's smallest integrated plug-in power solution, with a 6.7 mm 2 footprint and 90 mA/mm 2 power density. The power device combines all external components in a MicroSiP ™ package that has a 1mm height profile. Table 1 lists the fixed output versions of this power supply family.
Power efficiency is over 90% for a 600 mA load with a 2.3 V to 4.8 V input. In the past, portable equipment manufacturers had to design their own power supplies to meet space requirements. Now, the same manufacturers can use the TPS82671 instead.
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The TPS82671 is a synchronous dc-dc buck converter (Fig. 2a and Fig. 2b) with an integrated switching regulator, inductor and input/output capacitors. No additional components are required to complete the design. The TPS82671 is packaged in a 2.3 mm × 2.9 mm low profile (1.0 mm) BGA package suitable for automated assembly using standard surface mount equipment.
The TPS82671 operates at a regulated 5.5-MHz frequency with pulse width modulation (PWM) at moderate to heavy load currents. The converter uses a unique frequency locked ring oscillating modulator to achieve excellent load and line response. One key advantage of its non-linear architecture is that there is no traditional feedback loop. The loop response to change VOUT is essentially instantaneous. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency lock loop (FLL) holds the switching frequency constant over a wide range of operating conditions.
At light load currents, the converter automatically enters a power-save mode and operates with pulse frequency modulation (PFM) that reduces quiescent current to 17µA (typical). This low quiescent current allows it to maintain high efficiency at light loads, while preserving fast transient response for applications requiring tight output regulation. During the power-save mode, the converter operates in discontinuous current (DCM) single-pulse PFM mode, which produces lower output ripple than other PFM architectures. It leaves the PFM mode and seamlessly enters PWM operation at higher output currents.
Fig. 3 shows the circuit for the TPS82671. The MODE pin allows selection of its operating mode. Connecting this pin to GND enables the automatic PWM and power-save mode operation. Pulling the MODE pin high forces the converter to operate in PWM mode even at light load currents. In the PWM mode, efficiency is lower than the power-save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to PWM mode during operation, which allows adjusting converter operation to meet specific system requirements.
PWM allows the converter to modulate its switching frequency using spread spectrum techniques that enable simple filtering of switching harmonics to lower input and output noise in sensitive applications. Spread spectrumís goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar to white noise. The end result is a continuous spectrum with lower peak amplitude. This makes it easier to comply with EMI standards and power supply ripple requirements.
Most supplies use either fixed or regulated switching frequencies, depending on the output load. This can create high noise components at the fundamental switching frequency and its harmonics. Spread spectrum architecture varies the switching frequency by ±10% of the nominal switching frequency, significantly reducing the peak-radiated noise on both the input and output.
The TPS82671 has an internal soft-start circuit that limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance source powers the device. Soft-start system progressively increases the switching on-time from a minimum pulse-width of 35ns as a function of the output voltage. This mode of operation continues for 100ms after it is enabled. If the output voltage has risen above 0.5V (approximately), the converter increases the input current limit, enabling the power supply to come-up properly.
The TPS82671 integrates an input current limit to protect the device against heavy load or short circuits and features an undervoltage lockout (UVLO) to prevent the device from operating at low input voltages. Fully functional operation is permitted down to a 2.1V input.
Buck converters like the TPS82671 have a pulsating input current, so use a low ESR input capacitor to prevent large voltage transients that cause the device to misbehave or interfere with other circuits. For most applications, the input capacitor integrated in the TPS82671 should be sufficient. If the application exhibits a noisy or erratic switching frequency, try using additional ceramic input capacitors.
The TPS82671 converter employs a small ceramic input capacitor. When a ceramic capacitor is combined with trace or cable inductance, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Therefore, place additional “bulk” capacitance (electrolytic or tantalum capacitors) between the converter's input and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI.
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Using voltage mode control for the TPS82671 allows use of a small ceramic output capacitor (CO). For most applications, the output capacitor integrated in the TPS82671 should be sufficient.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions.
For optimum efficiency over the entire load current range, the TPS82671 converter requires a minimum output ripple voltage in PFM mode. The typical output voltage ripple is ±1% of the nominal output voltage VO. The PFM pulses are time controlled, resulting in a PFM output voltage ripple and PFM frequency that depends (first order) on the capacitance seen at the converter's output.
The TPS82671 buck converter is intended as a point-of-load (POL) regulator, operating standalone without requiring any additional extra capacitance. Adding a 2.2mF ceramic output capacitor (X7R or X5R dielectric) is generally acceptable for converter stability, but will not necessarily help in minimizing the converter's output ripple voltage.
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