Power Electronics

SoC Uses Powerline Communications to Control Embedded Applications

System-on-a-chip features programmable flexibility to configure embedded applications controlled by powerline communications, such as lighting, industrial control, automatic metering, home automation, and smart energy management.

At first glance, powerlines would appear to be a potential communications medium for command and control of external devices. This application is complicated because it is difficult to predict the quality and reliability of communications over existing powerlines because of the associated variables of noise, impedance and line quality. The Cypress Semiconductor Corporation's PLC (powerline communication) system, however, has overcome these operating conditions with a design that enables secure and reliable communications up to 11,500 feet.

As shown in Figure 1, a typical Cypress SoC consists of two subsystems on a chip: the PLC Core and PSoC® Core (programmable system-on-a-chip). Apart from the PLC SoC, there is an external Powerline Coupling Circuit that completes the required system hardware. The PSoC Core leverages the programmable analog and digital resources. The PLC core integrates the Powerline MODEM PHY and the Network Protocol. The PSoC core integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. Besides its flexibility and integration, this system offers reliability with 100% powerline data transmission success rates on standard networks and offers retries built into its coding in case data is dropped on noisy or low impedance networks.”

The system offers the flexibility to communicate over high-voltage and low-voltage powerlines for lighting and industrial control, home automation, automatic meter reading and smart energy management (Figure 2) applications.

PLC CORE

Adding the PLC Core to the Cypress SoC inserts the application coding obtained from the programmable analog and digital blocks and microcontroller of the PSoC architecture. This combination provides a single hardware platform for multiple applications, reducing BOM cost, board size and chip count while improving manufacturability. Included are:

  • Powerline modem (PHY) physical layer - based on Frequency Shift Keying (FSK) modulation
  • Configurable baud rates up to 2400 bps
  • Configurable Tx, Rx gains and Band In Use (BIU) threshold
  • Powerline optimized network protocol
  • Integrated data link, transport, and network layers
  • Bidirectional half duplex communication
  • 8-bit CRC error detection to minimize data loss
  • SPI, UART and I2C enabled powerline application layer

In the physical layer (PHY) shown in Figure 3, the digital transmitter serializes digital data from the network layer and feeds it to the modulator input. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic “1” or low level logic “0”. It then generates a square wave at 133.3 kHz (logic “0”) or 131.8 kHz (logic “1”), which is then fed to the programmable gain amplifier to generate FSK modulated signals that are applied to the Powerline Coupling Circuit. This enables tunable amplification of the signal. Using this amplifier, the amplitude of the signal coming out of the chip can be varied between 55 mV to 3.5V. This feature enables the PLC modem to communicate effectively even when the channel is noisy. The logic “1” frequency can also be configured as 130.4 kHz for wider FSK deviation.

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Incoming FSK signals (RX) from the Powerline Coupling Circuit are sent to a high frequency (HF) band pass filter that filters out-of-band frequency components and outputs a filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodulation. The mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies.

Intermediate frequency (IF) band pass filters further remove out-of-band noise as required for further demodulation. This signal is fed to a correlator that produces a dc component (consisting of logic “1” and “0”) and a higher frequency component.

The correlator output feeds a low pass filter (LPF) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. The hysteresis comparator digitizes LPF output, which eliminates the effects of correlator delay and false logic triggers due to noise. The digital receiver deserializes this data and outputs it to the network layer for interpretation.

In response to the requirements for the specific application, the PLC Core uses two-way communication with the PSoC core, which employs a highly configurable system-on-chip architecture for embedded control design.

PSOC CORE

The PSoC platform consists of controller devices that replace multiple, traditional MCU-based system components with one, low-cost, single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application.

Among the members of this family are cost-optimized fixed-function device with an I2C interface (CY8CPLC10), programmable PSoC-based devices (CY8CPLC20), and programmable PSoC-based devices optimized for LED support (CY8CLED16P01). The CY8CPLC10 is available in a 28-pin SSOP package, while the CY8CPLC20 and CY8CLED16P01 devices come in 28-pin SSOP, 48-pin QFN and 100-pin TQFP packages.

For example, the CY8PLC20 contains:

Programmable System Resources

  • Up to 14-Bit ADCs
  • Up to 9-Bit DACs
  • Programmable gain amplifiers
  • Programmable Filters and Comparators
  • to 32-bit timers, counters, and PWMs
  • CRC and PRS modules
  • Up to four full duplex UARTs
  • Multiple SPI masters or slaves
  • Connectable to all GPIO pins

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Flexible On-Chip Memory

  • 32 KB flash program storage 50,000 erase or write cycles
  • KB SRAM data storage
  • EEPROM emulation in flash

Additional System Resources

  • I2C slave, master, and multi-master to 400 kHz
  • Watchdog and sleep timers
  • User-configurable low voltage detection
  • Integrated supervisory circuit
  • On-chip precision voltage reference

POWERLINE COUPLING CIRCUIT

The Powerline Coupling Circuit (Figure 1) is an external unit that couples low voltage signals from the PLC Core to the powerline. Included is an isolated offline switch-mode power supply that operates from the same powerline that carries the communication signaling. The circuit meets the requirements for signaling on high voltage lines according to the EN50065-1:2001 and FCC Part 15 standard. It operates with 110V/240Vac and 12V/24V ac-dc powerlines.

The coupling circuit receives the FSK transmit signal, TX, originated in the PLC core as a low amplitude (~125 mVp-p configurable from 55mVp-p to 3.5Vp-p), unfiltered signal and applies it to the transmit filter and amplification block. The transmit filter is a fourth order Chebyshev response band pass filter, designed for 1.5 dB maximum pass band ripple. It provides 16.5 dB of gain at the center frequency of 133 kHz, suppression of -20 dBc at the 150 kHz band limit, and -50 dBc and -60 dBc at the second and third carrier harmonics, respectively. The transmit output signal drives isolation transformer T1 that connects to the powerline. A 1.0 µF capacitor (C14) removes the DC offset for the transmitter on the device side, and a 0.15 µF capacitor (C9) along with transformer T1 forms a high pass filter blocking the 50/60 Hz HV Powerline carrier signal and passing the 133 kHz PLC signal.

LOW IMPEDANCE

The receive signal is coupled from the line into the PLC Core via isolation transformer, T1, used by the transmitter. Transformer T1 must provide low impedance at the signal frequency and low leakage. An internal 0.01 µF capacitor provides dc isolation and a 2.0 kΩ input resistor sets the receiver's input impedance. This resistor, along with two diodes, provides signal limiting to protect the circuit from high amplitude transmitter signals and any large signals coupled in from the line.

The receive filter consists of a 1mH inductor, 150 pF capacitor and the 2.0 kΩ resistor. It rejects of out-of-band interference, such as AM broadcast signals that might be coupled from the line and could swamp the internal receiver circuit.

The offline switch-mode power supply is a standard isolated flyback converter using a full-bridge input rectifier. A 1.0Ω input resistor from the line provides in-rush current limiting. An MOV transient voltage suppressor provides against transients and an input fuse protects against an overcurrent condition. This power converter is intended for worldwide operation from line voltages ranging from 90Vac to 240Vac. This results in peak voltages approaching 350V dc, so the associated filter capacitors must be rated to safely accept these peak values.

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REFERENCE DESIGNS

Cypress provides reference designs for a range of powerline voltages including 110V/240V ac and 12V/24V ac-dc. The PLC system can provide data communication over other ac-dc powerlines as well with the appropriate external coupling circuit. The 110Vac and 240Vac designs comply with the powerline usage regulations.

Cypress also offers multiple evaluation and development kits. The CY3272 High Voltage Powerline Communication Evaluation Kit and CY3273 Low Voltage Powerline Communication Evaluation kits are compliant with FCC and CENELEC standards and includes an evaluation board, quick start guide, multiple cables, a USB cable, a 12V ac power adapter and a CD with test software, datasheets, a user guide, an application note, schematics and Gerber files.

The CY3274 Programmable High Voltage Powerline Communication Development Kit (Figure 4) and CY3275 Programmable Low Voltage Powerline Communication Development Kit enable system design using CY8CPLC20 devices. The CY3276 Programmable High Voltage Powerline Communication Development Kit and CY3277 Programmable Low Voltage Powerline Communication Development Kit are targeted for lighting application system design using CY8CLED16P01 devices.

Among the development tools are:

  • Free Development Software (PSoC Designer™)
  • Full Featured In-Circuit Emulator (ICE) and Programmer
  • Full Speed Emulation
  • Complex Breakpoint Structure
  • 128 KB Trace Memory
  • Complex Events
  • Compilers, Assembler, and Linker

SPECTRUM ANALYSIS

A spectrum analyzer was used to measure quasi-peak and average PLC signals, taken over a period of one minute. The test was conducted with both 110V and 230Vac mains. The PLC modem had the following settings for these measurements:

  • Transmit gain set to 125 mVp-p
  • Clocking mode set to external oscillator
  • Baud rate set to 2400 bps with a 1.5kHz bandwidth

A CY8CPLC10 chip was used in an internal test mode to continuously transmit data. The external I2C connection was not used to initiate transmission, because the unshielded connecting cable can generate excessive noise. In normal user applications, the I2C connection is usually on the same board and the system is in an enclosure. The graph in Figure 5 shows the results of the conducted emissions test with the chip mounted on a CY3272 evaluation board.

The dark red and blue lines show the output spectrum from 10 kHz to 24 MHz based on the quasi-peak and average measurements taken at the mains terminals of the device respectively. The light red and blue lines show the allowed limit of the spectrum as given in the EN50065-1:2001 standard for quasi-peak and average measurements, respectively.

The chip's peak output level is measured as 119.04 dBµV on the mains output of the board. The limit of devices that transmit in the frequency range of 95 kHz to 148.5 kHz is 122 dBµV. The peaks of the first and second harmonic signals are 57.67 dBµV and 39.59 dBµV, respectively.

NOISE IMMUNITY

Tests on a Reference Design Board illustrated the immunity of the CY8CPLC10 programmable system-on-chip to white noise and narrowband interference in the PLC communication frequency band. The interfering signals were chosen because they were known to be critical to the functioning of the PLC boards. The following types of interference were used:

  • White Noise
  • Single Tone Continuous
  • Single Tone Burst
  • AM Modulated

Cypress' PLC solution allows designers to integrate system functions and powerline communication functionality on the same chip. Before, system designers had to purchase different chips for their system functions. The basis for the Cypress solution is a SoC platform that allows designers to implement highly integrated designs with minimum components. This approach pays special attention to the PLC's performance, making it reliable to use under a variety of conditions.

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