The use of supercapacitors with LDOs, though simple enough to appreciate, has several implementation issues. Some of the important ones are:
- Buffer capacitor requirement and the associated energy losses due to paralleling of capacitances
- ESR losses in the SCs and the associated losses
- Unwanted discharge of capacitors due to body diodes. This issue comes up if discrete MOSFETs are used as switches.
PARALLELING OF CAPACITORS WITH UNEQUAL VOLTAGES
In the basic concept we try to discharge a supercapacitor, by changing the circuit configuration. During this process for continuity of the regulation, a buffer capacitor is required to supply the LDO during transition. However, this capacitor, which can be pretty small compared to the supercapacitor, may have a different terminal voltage at the time of transfer into the parallel mode. This will dissipate energy within the ESR components of the two capacitors. If two capacitors CS and CB with terminal voltages of VS and VB respectively are paralleled, the loss of energy due to paralleling is:
The Equation (1) indicates that higher the difference between the voltages or the loss, due to dissipation in their ESRs will be increased. However, if the buffer capacitor is very much smaller than the SC the loss is:
This indicates that if the buffer capacitor (CB) is very much smaller than the series SC, the loss can be relatively small.
In case where the two capacitors are at different voltages, to minimize the loss, it may be possible to monitor the two capacitor voltages and make transfer at a time when the two capacitors are nearly at the same voltage. Fig. 1 depicts a circuit that implements a solution, however with a slightly increased circulation frequency.
ESR LOSSES AND ASSOCIATED VOLTAGE DROPS
In this technique, we place a SC in the series path of the load current in part of the circulation cycle. The associated loss, IL × ESR, can create a voltage drop at higher load currents to push the LDO to an input voltage below its minimum VIN for proper regulation. Therefore, selecting SCs with very low ESR becomes an important factor. Energy losses associated with the ESR, similar to the case of switching power supplies, will contribute to the overall efficiency issue. However, as the switching cycle frequency is very low, this dynamic loss is very much smaller compared to the cases of switching supplies. Table 1 compares the popular DC-DC converter techniques
Table 2 compares SCs and electrolytic capacitors from a few suppliers, which clearly indicates that the ESR of new generation SCs are relatively small compared to common electrolytic caps.[8-14]
Due to the ESR voltage drops at higher load currents you may have to resort to a different configuration. For example, due to ESR drop issues, the 12V to 3.3V case may not be easily implemented based on the configuration suggested for the case of VS>3VIN(MIN). However, at high load currents, despite the ESR drops of SCs, and the on-resistance of the switches, a 12 V to 3.3 V regulator worked reasonably well under VS>2VIN(MIN) configuration. Results for the efficiency improvement and the transient response of a prototype 12 V to 3.3 V regulator are shown in Fig. 2. This configuration still has a significant efficiency improvement, reaching close to 50%, compared with the maximum theoretical efficiency of 27.5% for a 12 V to 3.3 V linear regulator.
UNWANTED CAPACITOR DISCHARGE
In implementing the technique, where in one phase of the operation we reverse the switches, if commercial discrete MOSFETs are used, the body diode may create unnecessary discharge paths and jeopardize the implementation. This is the reason we used solid sate relays in proof of concept circuits. In discrete implementations, one could use MOSFETs similar to RF power MOSFETs as they don't have the body diode. In IC versions of implementation, where switches can be developed without the body diode this problem will not be present.
Development of this technique can be easily applied to processor power supplies such as 5 V to 3.3V, 3.5 V to 3.3 V/2.2 V/1.8 V or 5 V to 1.5 V versions required by various processors. With the commercial LDOs available with output current ratings up to about 10A, and, very thin profile supercapacitors with DC voltage ratings from 2.3 V to 5.5 V, the technique allows developing medium current linear regulators that could compete with present day switch-mode power supplies. Due to very low frequency of capacitor circulation, dynamic switching losses in the devices are minimum, while creating no RFI/EMI issues - which creates significant issues in powering portable appliances with analog circuit blocks.
Versatility of this technique allows a wide range of supercapacitor-based linear DC power supply topologies, maintaining the advantages of linear power supplies, and eliminating the efficiency limitation. Also this provides a solution to the practical electromagnetic compatibility issues in switching regulator based systems.
Further development of this technique will also lead to developing high efficiency, low emission type voltage regulator circuits, based on linear regulators, to power very high current processors.
In the next developmental stage the research team at the University of Waikato, New Zealand wants to enter into collaborative work with commercial or research groups in the U.S., Asia or Europe, to bring the concept into monolithic IC form. Presently with the help of the commercial arm of the university, the team is communicating with research groups working in LDO research projects in other universities for collaborative research towards a monolithic IC fabrication based on our supercapacitor energy recovery concept. The U.S. patent was granted in March 2011. PCT patents are in progress.
Although work needs to be done, the results indicate that supercapacitors used with low dropout regulators (LDOs) can improve the efficiency of DC power supplies used in portable applications. In the first part of this article (Power Electronics Technology, April 2011, p. 14). it was shown that the low efficiency of linear regulators can be overcome using a patented, low frequency supercapacitor energy recovery technique. This technique is based on the hypothesis that the voltage change ΔV across a large capacitance (C) is very small when a finite charge (or discharge) current IL flows during a finite time Δt.
In the second part of the article, the issues related to implementing the supercapacitors with the LDOs in the DC power circuit were discussed. Design engineers need to consider the ESR characteristics of the supercapacitor and buffer capacitor and the energy losses associated with paralleling capacitors. In addiion, the unwanted discharge of capacitors due to body diodes must be considered, as in the case where discrete MOSFETs are used.
- B. Travis, “Linear VS Switching supplies: Weighing all the options,” EDN Magazine, 1998.
- O. Khorshid, “Selecting charge-pump DC/DC converters,” EDN Magazine, pp. 115, August 17 2000.
- N. Kularatna, “Electronic circuit design: From concept to implementation” pp. 150-160: CRC Press, 2008.
- High current voltage regulator, Application number 627542001000, 2008.
- N. Kularatna, and J. Fernando, “A supercapacitor technique for efficiency improvement in linear regulators.” pp. 132 - 135.
- N. Kularatna, J. Fernando, K. Kankanamge et al., “Very low frequency supercapacitor techniques to improve the end-to-end efficiency of DC-DC converters based on commercial off the shelf LDOs” in IECON ‘10, 2010.
- N. Kularatna, J. Fernando, K. Kankanamge et al., “Low frequency supercapacitor circulation technique to improve efficiency of linear regulators based on LDO chips” in APEC ‘11, 2011.