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Gain Equalization Improves Flyback Performance

In a discontinuous flyback converter, the gain of the output current is a function of the control voltage. A constant gain can be provided by compensating circuitry, which improves control-loop stability.

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The transfer function of the discontinuous flyback converter is such that the output current (IOUT) is proportional to peak current (IPK2); IPK2 is also proportional to on time (TON2), which is also proportional to control voltage (VC2), as shown in Fig. 1.

The open-loop gain, and therefore the bandwidth, varies directly with IPK, TON and VC. Using a logarithmic converter on VC can stabilize the gain, resulting in improved overall performance, because the bandwidth at low current is increased while keeping the high current gain at the maximum value allowed by the circuit.

Fig. 2 shows a “state-space” SPICE simulation of a multi-phase flyback converter.[1] The flyback block, shown as X1 with inputs VIN and VC and outputs VOUT and duty, linearizes the switching of the output power device (power MOSFET or BJT). This linearization enables SPICE simulations to run very quickly while still producing accurate line/load step, startup and other types of transient results, in addition to enabling the traditional small-signal ac analysis (Bode plot).

State-space techniques are a staple of power-supply designers who use SPICE.[2] State-space simulations allow SPICE to run as fast as or faster than many nonSPICE-based piecewise-linear simulators. The class of switching simulations where SPICE is at a disadvantage to periodic operating point/piecewise-linear simulators is truly very narrow. In addition, SPICE has the added advantage of much wider model support, and many average models for SPICE are readily available.

The flyback block and other state-space blocks for topologies, such as buck, boost and forward, can be found in the Power IC Model Library for PSPICE ( and in other literature.[3, 4]

Logarithmic Compensation

Fig. 2 shows the circuit with linear control, which results in the output current being proportional to VC2. From Fig. 3, E1 and E2 are used to force the current-mode state-space flyback model to operate in voltage mode. R1 through R8, D1, D5, D6, D7 and X6 comprise the log converter, which performs the gain equalization. The components were selected to adjust the converter's response to approximate the square-root function over the range of VC. VRAMP offset is the typical offset contained within most PWM integrated circuits. The transformers are ideal dc-dc transformers with a secondary-to-primary turns ratio of 0.25.

Fig. 4 shows the output current versus control-voltage response using normal linear gain control. The traces show the output current as a function of VC (trace 2) and the derivative of IOUT with respect to VC (trace 3), which is the gain. This graph clearly shows that the gain is linearly proportional to VC.

Fig. 5 shows the output current versus control-voltage response using logarithmic gain control. The traces show the output current as a function of VC (trace 1) and the derivative of IOUT with respect to VC (trace 2), which is the gain. This graph shows that the gain is relatively constant and nearly independent of VC over a wide operating range. Using a more accurate logarithmic control would provide a flatter gain curve.

The open-loop bandwidth of the control loop is directly proportional to the gain. This would mean that using the linear control results in a bandwidth tolerance of nearly 90% over the full operating range (~9 A/V average ±8 A/V) while the log control results in a gain tolerance of approximately 20% (~9 A/V average ±2 A/V) over the full operating range. The gain tolerance reduction offered by the log control makes it much easier to stabilize and also allows better closed-loop performance. This gain equalization could be done accurately with a square-root circuit; however, the approach presented here will work nearly as well.

Gain and Bandwidth

The main concern with the gain being proportional to VC or IPK is that the closed-loop performance of a converter is a function of its bandwidth. The result is that if the gain is a function of VC, then the closed-loop performance will be a function of VC (and, therefore, load dependent). The major performance characteristics affected are ripple rejection (and, therefore, the line-step response), output impedance (and, therefore, the step-load response), and the open-loop bandwidth and phase margin. In the case of line-powered flyback converters (nonPFC), the ripple rejection may be important to remove the 120-Hz ripple component from the output.

In order to tolerate a wide gain variation, it is generally required that the control loop have a very low-frequency zero to ensure single-pole compensation at the zero crossing (the single, dominant pole is usually the output capacitor). The overall effect of the low-frequency zero is a long response time. This requires, for example, that the soft-start time be very long so as not to result in output-voltage overshoot. The recovery time for load and line steps also will be long as a result of the low-frequency zero. Some applications may not be sensitive to these performance characteristics, in which case a low-frequency zero and a wide gain variation are not significant issues. In other cases, the open-loop performance can be improved, such as with larger output capacitors.

The addition of gain equalization allows the optimization of the control loop for the best performance in those cases that do require or demand it. In select cases, it may be the difference between whether a linear post-regulator is required, adding to the cost and reducing the efficiency of the power-conversion circuitry.

In specific applications, such as PFC converters, the bandwidth of the control loop must always be lower than the line frequency, or significant current distortion will occur. Further reduction of the bandwidth to accommodate the gain variation due to loading also will degrade the performance of the converter. For this reason, many of the PFC-specific control integrated circuits include a gain equalization network allowing the best performance possible, given the requirement for the low bandwidth necessary to achieve low line-current distortion.


  1. Sandler, Steven M. Switchmode Power Supply Simulation with PSPICE and SPICE 3, Chapter 5, McGraw-Hill, 2006, ISBN 0-07-146326-7.

  2. Basso, C. Switch-Mode Power Supply SPICE Cookbook, McGraw-Hill, ISBN 0-07-137646-1.

  3. PSPICE Power IC Model Library Documentation, AEi Systems, LLC, 2005.

  4. Amran, Y., Huliehel, F., and Ben-Yaakov, S. A Unified SPICE Compatible Average Model of PWM Converters. IEEE Trans. on Power Electronics, 6, 585-594, 1991,

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