Because of the widespread use of pulse-width modulation (PWM), the efficiency of a synchronous buck converter operating in this mode is well understood. However, relatively few designers understand how to predict the efficiency of a buck converter when it operates under pulse-frequency modulation (PFM), a mode that is widely used in portable applications to improve efficiency at light loads. Therefore, an efficiency analysis of PFM mode operation is quite useful, especially when using buck regulators that allow automatic switching between PFM and PWM modes.
To calculate the efficiency of a regulator operating in PFM mode, it is first necessary to identify and characterize the mechanisms that generate losses for this mode. This information may then be combined with a standard analysis of buck converter efficiency in PWM mode to predict system efficiency over the full operating range of the converter. The validity of this analysis can be verified by comparing predicted system efficiency with the measured efficiency for a synchronous buck converter capable of operating in both PWM and PFM modes.
Efficiency Analysis of a Buck Converter
In portable applications, efficiency, especially at light loads, has a significant impact on battery life. Normal PWM-mode operation can optimize efficiency at mid to full load, but this is usually at the expense of light-load efficiency. This could reduce overall efficiency in a system that frequently operates at light load. To maintain high efficiency across the entire load range, it is necessary to operate in PFM mode for light loads. System-level efficiency is further enhanced when the converter automatically selects between the two modes to give the best efficiency for any given load.
A typical synchronous buck converter is shown in Fig. 1. For PWM operation, losses of a synchronous buck converter can be grouped into two categories, dc losses and ac losses. The dc losses are determined mainly by on-resistance (RDS ON) in the low-side and high-side MOSFETs, and by the series dc resistance (DCR) of the inductor. The ac losses consist mainly of switching losses, gate-drive losses of both FETs and dead-time losses. The ac losses are proportional to the MOSFET switching frequency.
There are different approaches to improve the operating efficiency for different load ranges. Normally, dc losses dominate at heavy load, so lowering RDSON and DCR would effectively improve efficiency at heavy loads. However, at light loads, conduction losses become insignificant as the ac losses dominate, so decreasing the switching frequency effectively improves efficiency.
Another design consideration when synchronous buck converters operate at light loads is negative inductor current during synchronous operation. When the load becomes smaller and smaller, inductor current can change from positive to partially negative. This negative inductor current discharges the output capacitor and causes additional losses. Therefore, efficiency can be further increased by operating the converter in a nonsynchronous mode, in which a zero-crossing detection circuit would turn off the low-side n-type FET (NFET) when the inductor current goes negative.
PFM is a nonlinear operation in which a series of inductor current pulses are applied to the load and output capacitor to maintain the output voltage within preset boundaries. This mode effectively lowers the frequency of the switching-cycle events, thereby lowering the switching losses in the converter. There are several variations on PFM, such as single-pulse PFM, multipulse PFM and burst-mode PFM. However, all operate according to the basic principle of initiating switching cycles only as needed to maintain the output voltage.
PFM Burst and Pulse Frequencies
Typical inductor current and output-voltage waveforms during PFM mode are shown in Fig. 2. During PFM operation, a nonlinear bang-bang control is applied. In this control scheme, four boundary conditions regulate the output voltage: peak inductor current, zero-crossing detection of the inductor current, VOUT upper threshold and VOUT lower threshold.
When the p-type FET (PFET) in the Fig. 1 circuit turns on, inductor current will increase for time interval dt1 until it reaches the current limit. It is important to note that this current limit is set specifically for PFM mode, and is different from the overcurrent-protection threshold of the regulator.
where IPFM PEAK is the peak inductor current during PFM mode, VIN is the input voltage, VOUT is the output voltage and L is the inductance of the inductor. When the PFET turns off, the NFET turns on and inductor current decreases for time interval dt2 until it reaches zero. This action is described by the following equation:
Therefore, the pulse frequency (f1) is determined as:
The charge provided by the inductor pulses and the charge supplied by the output capacitor (COUT) to the load should be equal within a single burst period to maintain a stable dc output voltage across COUT in the Fig. 1 circuit. Therefore, the burst frequency (f2) is determined by:
where COUT is the capacitance of the output capacitor, T2 is the dead time, IOUT is the output current drawn by the load, and VR is the ideal ripple voltage of the output as defined by the upper and lower control thresholds.
Inductor conduction loss (PCONDUCTION INDUCTOR) is calculated as follows:
The inductor ac losses (PAC INDUCTOR) can be computed by the product of the inductor's ac-equivalent resistance (RAC INDUCTOR) and the root-mean-square (rms) value of the inductor current:
High-side PFET conduction losses (PCONDUCTION PFET) can be estimated as:
Because of the zero-crossing detection capability, when the high-side PFET in the Fig. 1 circuit turns on, inductor current is zero, which eliminates the turn-on loss. Therefore, only the turn-off loss for the PFET (PTURN OFF PFET) is considered:
where TTURN OFF PFET is the turn-off switching time for the PFET. Gate-drive loss for the high-side PFET (PGATE DRIVE PFET) is determined by gate-to-source capacitance (CGS PFET), input and output voltage, load current and the PFM preset current limit as follows:
Conduction loss of the low-side NFET in the Fig. 1 circuit (PCONDUCTION NFET) is calculated by the on-resistance of the NFET (RDS NFET) and the rms current through the NFET.
The gate-drive loss of the low-side NFET (PGATE DRIVE NFET) is obtained by:
Because of the dead time (T2 in Fig. 2), the shoot-through losses in the NFET and PFET are avoided, as well as the switching loss of the low-side NFET. Moreover, zero-crossing detection removes the turn-off switching losses and reduces the freewheeling current losses in the low-side NFET. So, the turn-on diode loss of the NFET (PDIODE LOSS NFET) is the only loss generated during the dead time of the PFM cycle:
where VDIODE NFET is the forward-voltage drop of the NFET body diode. The ESR loss related to the output capacitor (PESR CAPACITOR) and quiescent current losses (PIQ) are calculated using Eqs. 13 and 14, respectively:
where ESRCAPACITOR is the ESR of the output capcacitor and IQ is the quiescent current. The reductions in losses at light loads give the PFM-mode operation of the Fig. 1 circuit much higher efficiency than the forced PWM-mode operation.
One important parameter in PFM mode is the output ripple. Referring to Fig. 3, the time intervals that affect output ripple (tA and tB) are defined as follows:
Because of the charging balance of the output capacitor needed to maintain a constant value for VOUT:
where VRIPPLE is the actual ripple voltage on VOUT. Note that VRIPPLE is greater than VR. This is true because even when the output voltage reaches the upper threshold for VOUT and the PFET is off, the converter has no further control over VOUT. The output capacitor will continue to charge until the inductor current decays to the value of the load current. Therefore, the actual output peak is always higher than the upper threshold for VOUT.
Additionally, when VOUT reaches the lower threshold, the PFET turns on to pull VOUT up. The output voltage continues to decrease until the inductor current builds up to the value of the load current. Therefore, the actual minimum value for VOUT is less than the lower threshold for VOUT. Again, the cumulative result of these two control limitations is that VRIPPLE is greater than VR, affecting the number of switching cycles in a burst (N) as follows:
Rounding up the resulting N from Eq. 18 to the next-highest integer, output ripple is then given by:
Transition Between PFM and PWM
To optimize the system-level efficiency of the converter, it is best to change between PFM and PWM operating modes at the peak of the forced PWM efficiency curve. Then the combined PFM and PWM efficiency curve would be the profile of the higher efficiency between the two modes for each value of load current. Because input voltage has a strong effect on the PWM efficiency curve (Fig. 4), the value for the load current giving peak PWM efficiency decreases as input voltage decreases. Therefore, it is desirable to set different transition points for different input voltages. In general, the lower the input voltage, the lower the value of the transitional load current between PFM and PWM operating modes.
National's LM3677TL can be used to implement a buck regulator that automatically switches between PFM and PWM in the manner described previously. It is a 3-MHz buck regulator with 600-mA load capacity. Fig. 5 shows typical waveforms of this implementation in PFM-mode operation, implementing the following values for the buck topology shown in Fig. 1: VIN = 3.6 V, VOUT = 1.8 V, F = 3 MHz, L = 1 µH, CIN = 4.7 µF and COUT = 10 µF.
The table shows a sample comparison between the estimated and measured frequencies of PFM mode at VIN = 3.6 V, VOUT = 1.8 V and IOUT = 20 mA.
Fig. 6 shows an efficiency comparison between forced-PWM, and PFM and PWM operating modes. Good agreement is observed between measured and estimated results for the latter operating mode. The efficiency improvement using PFM mode is also illustrated clearly in this graph. For example, when the load current is 1 mA, PWM mode can only provide 8% efficiency. However, PFM mode can provide a substantial improvement, with 84% efficiency.
Fig. 7 illustrates the weighting of the various losses contributed by PFM mode and forced-PWM mode for a 10-mA load. Because of the low rms current in PFM mode, ac losses in the inductor are greatly reduced, and the high-side PFET turn-on loss is totally removed. As indicated in Fig. 7, PFET turn-on and turn-off losses, gate-drive loss and dead-time loss are also significantly reduced in PFM mode. It is all because of switching events.
Fig. 8 shows the burst-frequency change with the change of load. At no load, burst frequency approaches zero. As the load current increases, the burst frequency starts increasing and peaks at about half the maximum load current that PFM mode can support. Then burst frequency decreases to zero, at which point the device operates in PWM mode. This mechanism indicates that the PFM-mode operation results in an output voltage with very rich harmonics.
The increase in efficiency gained by using PFM mode is substantial and directly translates to longer battery life in portable applications. As demonstrated by the LM3677 design example, the efficiency of a synchronous buck regulator operating in both PFM and PWM modes can be predicted with a high level of accuracy.