Power supplies with N+1 redundancy require the use of an ORing diode or FET to isolate the main supply from the output bus in case of failure. Although ORing diodes are easy to use, the power loss they would cause in high-current supplies is usually unacceptable. Using ORing FETs rather than diodes offers much lower losses, but doing so comes at the expense of design simplicity. However, FETs have become much easier to use as a result of the introduction of controllers from several IC manufacturers.
There are still concerns about glitches that affect turning off the FET, especially in applications with synchronous rectification. Specifically, if the ORing FET is on when it should be off, even for a few nanoseconds, shoot-through currents or reverse-boost operation from synchronous FETs can occur.
Fortunately, a simple circuit, as shown in the figure, can be used to overcome these concerns. The circuit can be made from comparators, an op-amp and a few passive components, all of which are commonly used components (for higher bus voltages such as 48 V, components with the appropriate voltage ratings must be used). The circuit also uses a current-sense resistor and the high-voltage output from a transformer secondary, which is usually included among the outputs in most power supplies, especially high-current units.
Referring to the figure, the circuit monitors two parameters: the power-supply load current and the ORing FET drain-source voltage. The primary trigger mechanism is the load-current monitor, which detects the voltage across a sense resistor in the return current path to the power supply. When the output current drops to a predetermined level, say 5% of the nominal output current, the ORing FET is turned off. This action anticipates that the FET current is about to reverse, meaning the bus voltage is about to rise above the input, so the gate drive is disabled to turn off the ORing FET. A Schottky diode (D1) is placed across the FET to carry any lingering forward current.
The current threshold for turning off the ORing FET is adjustable. It should be below the maximum continuous current supported by D1. Even without D1, turning off the FET at a low current would have little effect on the system, since the other supplies on the voltage bus should easily be able to handle the resulting small-step current increase.
Resistor RSENSE is in the ground line of the power supply and converts output current into a small voltage. This voltage is amplified by op-amp U1, whose output is compared to a reference voltage by comparator U2. For the circuit in the figure, RSENSE is 3 mΩ and U1's gain is set at 100. The output of U1 is then 0.3 V for 1 A of output current. This voltage is divided by two-thirds and compared to VREF.
VREF is set to 0.2 V by either a voltage divider fed from VBIAS, or by a dedicated reference circuit. When the output current is less than 1 A, U2's open-drain output is pulled high, turning on Q1, which then turns off Q3.
The output current threshold at which Q3 turns off can be adjusted in several ways, such as changing the resistance of RSENSE, the gain of U1 or the voltage of VREF. The output voltage from U1 also can be used for current-limiting or droop-sharing applications, since it is proportional to the load current.
Monitoring the drain-source voltage of the ORing FET provides a secondary fail-safe mechanism by switching off the ORing FET when the drain-source voltage is reversed, which occurs in the circuit when VOUT+ > VIN+. Usually, the triggering threshold is slightly offset to cause early turnoff, compensating for switching delays in the ORing FET. This is accomplished in the figure's circuit with mismatched voltage dividers (one with a 2-kΩ resistor, the other with a 2.12-kΩ resistor).
Referring again to the figure, comparator U3 monitors the voltage difference across the ORing FET Q3 and drives Q3's gate to ground when VIN+ - VOUT+ ≤ 0.1 V. This fail-safe voltage-based control mechanism is actually the basis of conventional ORing FET control.
The ORing FET can be an n-channel (the device used for the circuit in the figure) or a p-channel device, depending on the drive voltages available. Usually, n-channel devices are preferred, because they generally have a lower on-resistance than p-channel devices of the same size. However, an n-channel FET requires a separate voltage source capable of driving its gate above the voltage on its source terminal, which is connected to the VIN+ input in this circuit.
Conveniently, a separate higher-voltage output is usually available in high-current power supplies (due to single-point failure concerns), and this output can be used to supply the higher voltages needed by an n-channel ORing FET. In this circuit, a high-voltage output ranging from 19 Vdc to 24 Vdc is fed to the VBIAS input. However, for high bus voltages on VIN+ and VOUT+, the use of a 20-V, zener-based clamping circuit is a good precaution for protecting the ORing FET against excessive reverse voltage.