Although new technologies based on digital power control promise to be disruptive technologies in the long run, mainstream analog control technology can still have a significant and immediate impact on power system designs. Such can be said for this year's Power Electronics Technology Product of the Year award winner. The TPS40140 synchronous PWM controller from Texas Instruments (TI) is, at heart, an analog controller. However, because of its clever design techniques, the chip simplifies the potentially complex task of paralleling voltage sources to create scalable point-of-load (POL) power designs.
The TPS40140 features a unique characteristic that the vendor calls “stackability.” That term describes the way multiple controller ICs can be combined in a single design either to scale current levels on a given output or to add additional voltages. A single TPS40140 can be configured to generate two independent outputs or configured as a 2-phase controller with a single output. Then, by stacking or paralleling controller chips, designers can increase current output on a given voltage rail. The controller supports up to 16 phases of interleaved operation for up to 320 A of output.
The resulting design can be a mix of single- and multi-phase outputs (see the figure). Interleaved operation not only permits the scaling of current levels, but also reduces ripple current and requirements for input and output capacitance.
Although existing multiphase controllers can be cascaded to scale the number of phases, they typically employ an analog interface to control phasing of the different outputs. In contrast, the TPS40140 employs a unique digital interface to control phasing, which makes the designs less sensitive to noise and eases pc-board layout.
In a multicontroller, multiphase design, one channel generates a master clock (CLKIO). This clock is distributed to the slave channels, which use it to generate their PWM clocks. The master clock runs at eight times the frequency of the slave PWM clock. In other words, within each master clock signal there are eight frames (seven clock pulses plus a missing pulse for synchronization), and each PWM slave clock will trigger on a different frame depending on the phase number assigned to that PWM channel. That phase number is programmed using a simple voltage divider connected to the phase select pin on each channel.
In designing this part, TI overcame several design challenges. According to Stefan W. Wiktor, dc-dc controller design manager at TI, one of the most difficult was achieving good current balance among phases when the phases are generated across multiple controller chips. This is because of the difficulty in matching PWM ramp signals from chip to chip. TI addressed this problem using a frequency-to-current converter that makes the PWM ramp signal independent of semiconductor process-related parameters, except for reference voltage, which is very controllable.
Though just introduced in August 2006, the TPS40140 has already experienced design wins at two major power-supply companies, a large server manufacturer and a test equipment manufacturer. However, Tim Goodrow, product marketing manager for dc-dc modules at TI, observes that customers are adopting the TPS40140 because of the ease with which this controller implements multiphase control, more so than for its flexibility in generating multiple voltages.
Goodrow also notes that the part has been achieving exceptional performance in balancing current among phases. “Our load share scheme is working beyond our expectation,” he observed. “Our applications engineers have done module designs where the master-to-slave current-share accuracy error is much better than 5%.”
For more details, see “Controller Generates Multi- and Single-Phase Outputs,” Power Electronics Technology, August 2006.