Over the past few years there has been a big push by some environmental agencies to have off-line ac-dc power converters include power-factor correction (PFC). It started with the European Union's EN61000-3-2 input-current harmonic content specifications for power converters. Even though this was not a power factor specification per se, power-supply designers found it easier to meet this requirement with PFC preregulators. So this specification was a driving force for off-line power converters to have PFC.
In the United States, electric utilities have been sponsoring the 80 PLUS incentive program, which offers a cash rebate for power converters that are greater than 80% efficient with a power factor of 0.9 at full load. Having PFC preregulators in off-line power converters helps the power company greatly by reducing losses in the transmission lines and also by making better use of the available line power.
However, this benefit does not come for free and has created many challenges for power-supply designers. The PFC preregulator makes the off-line power converter less efficient, which makes it more difficult for some designs to meet the higher efficiency requirements of 80 PLUS. Fortunately, there are several innovative control techniques that make PFC preregulator designs more efficient.
The Efficiency Penalty
It is no secret to the utilities that PFC reduces transmission line losses by reducing line root-mean-square (rms) currents caused by ac-dc power converters. However, off-line power converters with PFC are generally less efficient than a well-designed power converter without PFC.
Typically, off-line converters with PFC are done with two power stages. Stage 1 is generally a boost converter that uses average current-mode control techniques to shape the input current. Stage 2 is a stepdown converter that steps the boost voltage down to a more usable voltage (Fig. 1). The overall total system efficiency (ηTOTAL) is the product of Stage 1's efficiency (ηSTAGE1) and Stage 2's efficiency (ηSTAGE2), which makes for an overall less-efficient power supply:
ηTOTAL = ηSTAGE1 × ηSTAGE2.
A large contributor to losses in traditional PFC preregulators is the reverse-recovery current in the boost diode. The following equation describes the switching losses in the boost diode at a given switching cycle due to reverse-recovery current:
where ID is the peak diode current, tRR is the boost diode's reverse-recovery time and fS is the switching frequency at which the boost converter is operating.
One PFC control technique adopted to remove reverse-recovery losses was the transition-mode PFC preregulator. This PFC boost preregulator incorporates zero-current switching to remove the reverse-recovery losses in the boost diode. The transition-mode PFC preregulators have zero-current detection that waits for the inductor to completely de-energize before turning on the boost FET for the next switching cycle. This technique uses pulse frequency modulation (PFM).
When designed correctly, the transition-mode PFC preregulator will have an inductor with a similar volume to the inductor used in an average current-mode control preregulator, but with no reverse-recovery losses in the boost diode. This characteristic also allows the designer to use inexpensive diodes. However, this topology does have some limitations. For example, the inductor ripple current is twice the average input current, which results in higher boost inductor and boost capacitor rms currents. These higher currents generally limit this topology to applications under 400 W (Fig. 2).
Another major contributor to the losses in a PFC preregulator is the boost FET's switching losses. The following equation is an approximation of FET switching losses (PQ1SWITCHING) in a given switching cycle:
where VBOOST is the PFC output voltage, ID is the peak FET and diode current for a given switching period, fS is the FET's switching frequency, and tR and tF are the FET's drain-to-source rise and fall times, respectively. COSS is the FET's total drain-to-source capacitance, VG is the maximum voltage applied to the gate of the FET and QG is the FET's total gate charge.
Traditionally, PFC preregulators are designed to have a fixed output voltage (VBOOSTFIXED) that needs to be set higher than the peak input voltage. When the converter is operating at low line input, this high output voltage is greater than it needs to be and penalizes the converter's overall system efficiency. In Stage 2, the input to the downstream converter does not need a fixed input and can easily handle a 3:1 variation in input voltage.
To improve efficiency and reduce switching losses, a technique was developed called a PFC boost follower. This technique exploits the fact that a PFC preregulator generally is in a two-stage power system and does not require a fixed output voltage. The boost follower converter is designed to have the boost voltage (VBOOSTFOLLOWER) track changes in line voltage to improve system efficiency.
To alleviate the stress of holdup requirements on the boost capacitor, these converters typically are designed to have the minimum boost voltage (VBOOST) set to be at least twice the peak input voltage at the minimum input line voltage. The boost follower's output will then increase and decrease with changes in line voltage to ensure the highest efficiency possible. Fig. 3 provides a graphical comparison of output voltage versus line voltage for a fixed output-voltage PFC boost and for a PFC boost follower.
The boost-follower innovation in PFC control greatly reduces switching losses but has one major limitation. This design typically requires four times the holdup capacitance of a fixed output-voltage PFC preregulator for universal applications where the input voltage varies 3:1.
Another promising topology for reducing losses in PFC preregulators and improving efficiency is the semi-bridgeless PFC preregulator (Fig. 4). This topology does require two boost stages, boost 1 and boost 2, where the boost inductors are tied directly to the input of the converter. It also requires a full-wave rectifier (DA, DB, DC and DE ) to peak charge the common PFC boost capacitance (CBOOST ) during initial power-up.
However, after the boost capacitor has been peak charged, and the converter is up and running, the power converter only requires one rectifier diode at a time (DA or DB) in the diode bridge to conduct for proper operation. This is different from the traditional PFC boost, where two of the bridge rectifier diodes are always conducting. This innovative technique improves efficiency by removing the conduction losses of one rectifier diode, which improves overall system efficiency.
Interleaved Boost Stages
The latest innovation in PFC control is interleaved PFC boost stages. This control technique requires that two power-factor corrected boost stages operate 180 degrees out of phase. There are many benefits of this topology that have made it so popular. One of the major benefits is the input and output inductor ripple current cancellation — if designed correctly, it can reduce total boost inductor and EMI volume. The output inductor ripple current cancellation reduces the boost capacitor rms current, which can lead up to a 25% reduction in capacitor volume. This is not to be confused with the amount of boost capacitance the design requires for holdup. This is typically determined by holdup time and output power. Fig. 5 shows a functional schematic of an off-line power converter with interleaved PFC preregulator (Stage 1).
Another major benefit, interleaved PFC preregulators can reduce conduction losses by up to 50% when compared to a single-stage power-factor-corrected converter. This can be observed by comparing the conduction losses for a single-stage PFC (PCONDUCTIONSINGLE) to the total conduction losses of an interleaved PFC (PCONDUCTIONINTERLEAVED). The reduction in conduction losses should make the interleaved PFC preregulator more efficient at higher power levels, where conduction losses dominate. This helps to improve maximum load efficiency in the off-line converter:
Even though interleaving PFC preregulators can improve efficiency where conduction losses dominate over switching losses, interleaving preregulators can decrease light-load system efficiency where switching losses dominate (PSWITCHING). This added loss is mainly due to the increased FET COSS and gate-drive switching losses. The following equation is an approximation of total boost FET and boost diode switching losses for an interleaved PFC preregulator for a given switching cycle:
where VG is the maximum gate voltage applied to the gate of the FET during activation and QG is the total gate charge at the maximum gate voltage.
To improve the interleaved PFC preregulator's efficiency, a control technique called phase management was developed. This technique requires control circuitry to monitor the converter's output power and turn on and off interleaved PFC phases based on the total loading of the converter.
At higher power levels where conduction losses dominate, the control circuitry has both phases enabled to reduce conduction losses. At lighter loads where switching losses dominate, the control circuitry turns off one of the phases and goes into single-phase operation. This reduces switching losses and makes it easier for the design to meet 80 PLUS light-load requirements.