Electrical overstresses can cause failure, permanent degradation or temporary erratic behavior in electronic devices or systems. The trend to reduce circuit geometries for communication systems and applications results in an increasing sensitivity to electrical transients. Suppressing these transients can challenge designers because the origin and severity of the overvoltage may be unknown.
When designing an electronic circuit or defining a complete system, it is important to identify the sources of those stresses and correctly understand their mechanism to properly define the environment of the operating system. In doing so, you can define simple design rules to adequately protect sensitive electronic systems with cost-effective solutions.
Power over Ethernet (PoE) equipment represents one class of systems in which sensitive power circuitry must be protected. Although PoE specifications provide for overcurrent protection, these systems are still vulnerable to the same electrical transients that can damage other types of power equipment.[1-2]
In PoE equipment, power-sourcing equipment (PSE) delivers power to a powered device (PD) via an Ethernet cable. The power is delivered through a difference between the respective common-mode voltages of the two twisted-wire pairs used for the two data channels in the Ethernet cable, as shown in Fig. 1. Even more power can be supplied with the additional use of the two spare twisted pairs. PoE applications are found in environments ranging from offices to industrial networks. Ethernet cables or equipment installations are usually located indoors but can be outdoors.
Transients in PoE Applications
Many standards have been developed to simulate or represent the transient overvoltage environment in various applications. For example, as per IEC transient immunity standards, transients can be classified into three categories:
- IEC 61000-4-2: Electrostatic Discharge (ESD)
- IEC 61000-4-4: Electrical Fast Transient/Burst (EFT)
- IEC 61000-4-5: Surges.
These IEC standards also define immunity test methods that apply to each transient category, and they also provide manufacturers of transient suppression components some standardized waveforms and overvoltage levels to which their components can be characterized and specified.
ESD is caused by the buildup of an electrical charge from the contact and separation of two nonconductive materials, followed by the release of the corresponding energy when the charged body is brought in proximity to another object of lower potential. For example, a person walking across a carpet can produce a charge of more than 15 kV.
ESD is a common-mode electrical event and is a discharge from one unit through an electrical path in the other unit, ultimately terminating through a chassis ground. An important design guideline is to clearly identify the path taken by the current and make sure it will not be harmful to the sensitive circuitry. An even better option is to provide an alternate path for the discharge current to bypass this sensitive circuitry.
The IEC 61000-4-2 standard simulates an ESD event from a person holding a metal object, referred to as the human metal model (HMM). Discharge may occur through direct contact (contact discharge) or proximity (air discharge). Table 1 shows the waveform parameters of the ESD generator in contact mode. The rise time is less than 1 ns for this mode. Total duration of the current pulse is around 150 ns.
Another threat is a cable-discharge event. This occurs when an Ethernet cable becomes charged, and then discharged into a circuit when it is connected to the cable. The cable could be charged by tribocharging (e.g., dragging it on the carpet) or induction (e.g., from a charged person holding it). A standard to define cable discharge with a specific test method has not yet been established. Most manufacturers use internal cable discharge event (CDE) test setups to evaluate their designs. A few deem it sufficient to test to the IEC Level 4 specifications to protect against such discharges.
However, the idea of equipment being able to withstand CDE if it passes IEC 61000-4-2 Level 4 discharges is not always true. This is because the charged capacitances in the two tests are very different, which is 150 pF for IEC ESD versus much larger capacitance for CDE, depending on the length of the cable involved and the cable elevation over the earth ground. There is also a transmission-line effect with some distributed capacitance as opposed to a lumped capacitance. CDE discharges typically dump more energy into the equipment under test than IEC Level 4 discharges.
Electrical Fast Transient
An electrical fast transient (EFT) is a result of arcing contacts in switches and relays, motors and other inductive loads; this is common in industrial environments. Normally, this type of transient is common mode and is introduced on telecommunication cables by capacitive coupling. IEC 61000-4-4 defines this transient as a series of very brief high-voltage spikes occurring at a rate of 5 kHz to 100 kHz. Severity test levels are summarized in Table 2. Short-circuit current values are estimated by dividing the open-circuit voltage by the 50-V source impedance.As per IEC61000-4-4, a capacitive-coupling clamp over the communication cable is the preferred method to couple the test voltage in communication ports. This includes an Ethernet cable, which means the coupling is done without any galvanic connection to the port. Another acceptable method of coupling is directly through a 100-pF discrete capacitor. It is worth noting that, because of its repetitive nature, EFT events also can result in the erratic behavior of a communications system.
Electrical-surge transients are the most severe in terms of peak current and duration, and the least severe in terms of rise time. They are caused by lightning strikes (either by a direct strike or by induced voltages and currents due to an indirect strike) or the switching of power systems (including load changes and short circuits). The degree of severity of the transient can change depending on whether or not the cable installation is inside or outside the building. IEC 61000-4-5 defines this transient as two surge waveforms: the 1.2 3 50-µs open-circuit voltage waveform and the 8 3 20-µs short-circuit current waveform.
IEC 61000-4-5 Classes 3 to 5 apply to outdoor applications, higher threat-level conditions and some particular indoor installations. In the majority of PoE applications, only indoor cable installation is considered. Also, the IEEE 802.3 standard requires the networks to withstand a 1500-V dielectric test-to-earth. In this article, only Class 2 (semiprotected environments) for unbalanced/balanced data lines have been considered. This corresponds to a rating of 1 kV/24 A for line-to-ground or 500 V/12 A for line-to-line. Other possible standards include the following ITU-T recommendations: K.20, K.21, K.44, K.45 and, in some cases, the GR-1089-CORE (intrabuilding lightning-surge specification).
Transients Protection Circuit Guidelines
The protection circuit should not interfere with the normal behavior of the circuitry to be protected. It must also prevent any voltage transient from causing an erratic, repetitive or not, behavior of the complete system. To meet these requirements, many guidelines can be applied to the design of voltage-transient protection for electronic systems.
A transient-voltage source may be a differential or common-mode type, or both. The categories of protection techniques against transient voltages are shielding and grounding, filtering, electrical isolation and the use of nonlinear devices such as diodes. Effective circuit protection results from a combination of blocking and diverting techniques. The use of common-mode chokes may be necessary, but the design chosen for the voltage suppressor must still have the speed and robustness required for the application. For example, shunt (line-to-earth ground) capacitors that may take a direct transient hit should be rated for high voltage (more than or equal to 2 kV) with low ESR.
There are also nine basic pc-board layout rules that improve transient protection. The first is to define a low-impedance path to divert any transient current or voltage away from sensitive components. Otherwise, an ESD current could cause severe damage as it seeks the earth ground of the system. Having a solid, low-impedance earth-ground connection directly on the pc board is the next rule. The third rule is to keep transient current density and current path impedances as low as possible using multipoint grounds where the current is designed to flow and single-point grounds where it is not. Keeping the loop within which the fast-rising currents must circulate small is the fourth rule. For fast transients, this is accomplished through the use of ceramic capacitors between the load supply point and ground whenever necessary, particularly when clamping diodes are tied to the power-supply rail.
The fifth rule to be applied during the circuit layout process is to physically isolate high-voltage or high-current transient areas from sensitive circuitry, even though these areas must be in close proximity to the I/O connectors. Specifically, locate high-current suppressors in the I/O areas, as well as switches, LEDs and displays. For the sixth rule, place all connectors on one edge of the circuit and sensitive circuitry at the center of the pc board, if possible. For the seventh rule, each protected signal should be routed from the suppressor circuit to the sensitive circuitry in parallel with its individual return signal to prevent any inadvertent transformer effect. The eighth rule is to ensure the suppressors use surface-mount packaging, and that four-terminal connection is used to mitigate the effects of parasitic inductances. Similarly, the ninth and final rule is to ensure that the pc-board layout does not introduce any parasitic capacitances that bypass transient-blocking series elements. However, having parasitic inductance in series with blocking series elements is not a concern.
PoE Circuit Protection
Although only secondary protection, usually deployed within the equipment to be protected, is discussed in this article, it should be noted that primary telecommunications protectors are required for outdoor telecommunications cables.
In PoE applications, PSE is powered from a 48-V power supply. Normally, this has some common-mode capacitances connected to earth-ground. Those capacitances can be either discrete capacitors, interlayer capacitance in the pc board or a combination of both types. Since the PSE is not really floating, any common-mode voltage transient applied on the data connector can result in a voltage breakdown of PSE components. This is especially true for a PSE port power-switch transistor. Fig. 2 shows this effect, along with the high-current path, which results in the destruction of the PSE power switch transistor when protection is not implemented. CCM represents the common-mode capacitance between the 48-V lines and chassis ground of the system. This can be either on the positive or negative (48-V return) line of the 48-V supply. To simplify the schematic, CCM is shown only on the negative line. This configuration is applicable when the ac-disconnect circuitry is used, which requires the use of D1. This operation of ac-disconnect circuitry results in the worst-case condition for transient protection.
In an application where RJ-45 cables are used, the previously mentioned protection technique of cable shielding is usually not an option. However, the solution in Fig. 3 adequately protects the PSE integrated circuit. This circuit applies when ac-disconnect circuitry is used. If it is not used, then D1 and D3 are not needed.
Key Component Parameters
It is important to consider the key parameters for each of the following major elements of this protection circuit. For clamping diodes D2 and D4, the key parameters are forward-recovery time, transient-current capability and forward-voltage transient. The TVS diode D3’s key parameters are response time, current-handling capability and low impedance. D3 is required only if D1 is used for the ac-disconnect function.
If more severe surges need to be considered, such as those defined in the GR-1089-CORE (intra-building lightning surge spec) standard, use more robust components for D2, D3 (1500-W TVS) and D4. Schottky diode D1 is required for negative-voltage transients. Bob Smith (BS) terminations or line-to-ground capacitors are also needed, because the initial ESD/EFT transients circulate through those terminations to earth ground.
Other major elements are the ferrite beads FB1 and FB2. These provide blocking impedances that prevent C2 from short circuiting the terminations at high frequency. The decoupling capacitor on the 48-V bus (100 nF) and the capacitor bridging the P and N terminals of the TPS2384 must be low-impedance ceramic types. C1 and C2 must be very close to the clamping diodes D1 and D2. The TVS diode on a 48-V bus (D5) is usually placed close to the 48-V input connector. All devices should be housed in surface-mount packages with low parasitic inductances.
Protection components keep any transient current from flowing through the N-to-RTN path or the P-to-RTN path of the TPS2384 IC, in either positive or negative polarity. However, those transient currents may follow different paths depending on the source of the transient. The case of protecting ESD or EFT, which are fast common-mode events, are illustrated in Figs. 4 and 5, respectively.
The dc-voltage level on C1 and C2 immediately prior to the transient event directly affects the paths that those transient currents will take. On ESD or EFT simulations, BS terminations — along with the ferrite beads — play a role in ESD/EFT suppression. BS terminations are also used for EMC reasons. These capacitors clearly define the first path that an ESD or EFT strike will take.
Simulations can provide an indication of the voltage magnitudes that are possible with various transient events. The maximum possible voltage on a line-to-earth-ground capacitor is around 1 kV, making a capacitor rated for 2 kV a safe choice. Simulations also indicate that with 8-kV ESD applied, with a 150-pF/330-V HHM, the resulting voltage across the 1-nF capacitor of the BS termination is less than 100 V. The highest voltage applied to this capacitor occurs during the surge test, which is 1 kV for a Class 2 event. Similarly, a 200-V rating for the 10-nF capacitor is a safe choice. However, because an ESD cable-discharge model has not yet been defined, no such simulation has been performed. A suggested board layout for a quad-port PSE that meets all the previously stated guidelines is shown in Fig. 6.
Clearly, D2, D4, D3, D1, C1, C2 and the power input and RJ-45 connectors must be very close together in order to keep the area of the transient-current loop and its resulting impedance as small as possible. In applications with multiple ports, it is recommended to have one decoupling capacitor equivalent to C1 per group of two or four ports, and to place each capacitor close to its associated group. It is also important to provide sufficient copper area for the suppressor device in order to facilitate heatsinking. One additional note is that Ethernet interface circuitry usually requires data-line protectors for the data-line driver circuitry. However, this article has focused on protection techniques applicable to PoE circuitry.
1. Standler, Ronald B., Protection of Electronic Circuits from Overvoltages, Dover Publications Inc., 2002.
2. Electrical transient immunity for PoE, http://focus.ti.com/lit/an/slva233a/slva233a.pdf.
3. IEC 61000-4-2, 61000-4-4, 61000-4-5, www.iec.ch.
4. ITU-T recommendations K.20, K.21, K.44 and K.45, www.itu.int/home/index.html.
5. Telcordia GR-1089-CORE, Issue 4, http://telecom-info.telcordia.com/site-cgi/ido/index.html.
6. Semtech AN96-07, TVS Diode Application Note, Revision 04/04/2002, www.semtech.com.