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As the dcdc conversion industry proceeds toward the demand for improved power density and efficiency, thermally enhanced packages with SO8 footprints have been gaining prominence and popularity in dcdc converter designs. These packages bring thermally superior, higher power devices to the SO8 footprint, enabling more efficient designs with a reduced profile. However, package parasitic effects in the standard SO8 are not clear due to various MOSFET characteristics such as threshold voltage (V_{TH}), package parasitic inductance, onresistance (R_{DS(ON)}) change, driver capability and layout.
But, by utilizing the efficiency data and switching waveforms of nearly identical silicon operating in SO8 and Siliconix's PowerPAK SO8 packages in a twophase synchronous buck converter, the package parasitic effects become more apparent. The results show that the package parasitic effect mainly depends on the package parasitic inductance and the MOSFET R_{DS(ON)} shifts from increased junction temperatures (T_{J}) determined by thermal characteristics of the package.
Package Comparison
The PowerPAK SO8 utilizes the same footprint and pinout as the standard SO8, as shown in Fig. 1. The only difference is the extended drain connection area. This allows the PowerPAK SO8 to be substituted directly for a standard SO8 package. The bottom of the dieattached pad is exposed to provide a direct, lowresistance thermal path to the substrate on which the device is mounted. This decreases the thermal resistance between the foot of the PowerPAK and the printedcircuit board (PCB).
A basic measure of a device's thermal performance is the junctiontofoot thermal resistance (R_{θ_JF}). This parameter is measured with the device mounted to an infinite heatsink and therefore is a characterization of the device only; in other words, the device is independent of the properties of the object to which it is mounted. The PowerPAK SO8 package has a junctiontofoot thermal resistance of 1°C/W. This parameter is 13°C/W for the standard SO8 package. The PowerPAK has thermal performance equivalent to the DPAK and an orderofmagnitude better thermal performance over the SO8, assuming that the silicon devices are identical in both the PowerPAK SO8 and standard SO8 packages. Again, the PowerPAK SO8 package allows heat to dissipate directly from the bottom of the package because the underside of the drain leadframe is directly exposed, resulting in a lower junctiontofoot thermal resistance.
In the SO8 package, cooling is less efficient because of the presence of the mold compound that covers the top and bottom of the silicon. In this package, the majority of the heat is dissipated through the mold compound into the PCB and the air.
Fig. 2 shows a crosssectional view of the PowerPAK SO8 and standard SO8 packages. As shown in the figure, the drain and source leadframe length in the PowerPAK SO8 is thinner than the standard SO8. That's why the PowerPAK SO8 has a reduced height and package inductance compared to the standard SO8. Using simulations of the two package types at direct current, 100 kHz and 1 MHz yielded parasitic inductances of 0.5 nH, 0.3 nH and 0.24 nH, respectively, for the PowerPAK SO8 package. The same values for the standard SO8 were 2.21 nH, 2.12 nH and 1.79 nH.
Device Characteristics
To explore the difference in performance between the two packages, identical die were assembled in a PowerPAK SO8 package and a clipattached SO8 package. Devices for both packages were selected carefully wafertowafer to minimize parameter variations. The MOSFET parameters for the selected devices are shown in the table.
For the standard SO8 packages, the Si4336 was chosen for the lowside MOSFET, and the Si4390 was chosen for the high side. The selected Si4336 and Si4390 devices were screened to keep variations within 5% in the SO8 package. The same screening was conducted for the devices mounted within the PowerPAK SO8 package (Si7336 for the low side and Si7390 for the high side).
Test Circuit Description
The test circuit used to evaluate a performance comparison in the PowerPAK SO8 and standard SO8 was a twophase synchronous buck converter. There were two highside devices per phase and two lowside devices per phase, totaling eight MOSFET devices on the board. The circuit accepts an input voltage of 12 V to 19 V. The output voltage was 1.3 V, and a voltage of 5 V was applied to the gatedriver supply. An automatic efficiency test tool was used to characterize efficiency and loss in the test platform. The automatic efficiency tool monitored all necessary node voltages and line currents for the efficiency calculation. The tool acquires data by performing 10 samplings for a given load condition. For each measurement, the maximum and minimum values are removed from the data set, and the average value of the eight remaining samples is then taken as the actual value of the measurement. The tool allows the converter to run for 500 sec for thermal stabilization of the board prior to executing efficiency and temperature measurements.
Fig. 3 shows the finished demo board. The PCB was a twolayer, 2oz copper board sized at 14.9 cm × 8.7 cm. While the converter was designed as a fourphase synchronous buck, only two phases were used in the test. A 0.68µH output inductor was selected to optimize performance of the switching regulator. A smaller value would have caused a highinductor ripple current that would have resulted in lower efficiency. A larger value would have slowed the transient response of the pulsewidth modulated controller. Schottky diodes typically placed across the lowside MOSFETs were omitted to ensure an accurate comparison of the performance between the SO8 and PowerPAK SO8 package types.
PowerPAK SO8 and SO8 Efficiencies
Neither a heatsink nor a forced airflow were used for the measurements of the package parasitic effects. Practical switching frequencies of 300 kHz and 500 kHz were chosen because they are widely used in VRM and pointofload applications. The converter packaged in the PowerPAK SO8 showed higher efficiency than the one in the SO8 package. In Fig. 4, the PowerPAK SO8 efficiency was 0.8% higher than that of the SO8 at 43 A. The difference in efficiency between the two packages increased with frequency. This indicates that the PowerPAK SO8 package is more efficient than the SO8.
Conduction Loss in LowSide Device
There are two major sources of loss in dcdc converters. One is conduction loss; the other is switching loss. The conduction losses result from R_{DS(ON)} of the devices and may be calculated by I_{LOAD}^{2} × R_{DS(ON)} × D for the highside MOSFETs, and I_{LOAD}^{2} × R_{DS(ON)} × (1  D) for the lowside devices, where D is the duty cycle and equals 10.8%. The change in MOSFET R_{DS(ON)} with temperature must also be taken into account, since the R_{DS(ON)} increases by the factor of 1.3 at T_{J}=100°C (Fig. 5).
Fig. 6 shows the foot temperature measurements on the lowside devices, taken close to the source terminal of the devices on the PCB. Although this is not an absolute measurement of the junction temperature, it is a close approximation. The results show that the PowerPAK SO8 is 91°C, while the standard SO8 is 101°C, where V_{IN} = 19 V, V_{OUT} = 1.3 V, f_{SW} = 500 kHz and I_{LOAD} = 43 A. The standard SO8 die temperature is 10°C above the PowerPAK SO8. Using the junctiontofoot thermalresistance characteristics of the PowerPAK SO8 and the standard SO8, the silicon's R_{DS(ON)} would be 1.25 × R_{DS(ON)} for the PowerPAK and 1.3 × R_{DS(ON)} for the standard SO8 under the same condition of I_{LOAD} = 43 A, as shown in Fig. 5, which applies because the sum of the two drain currents equals the load current of 43 A. Each drain current is then 21.5 A, which is sufficiently close to 25 A. Thus, the conduction loss R_{DS(ON)} in the PowerPAK SO8 is 4% less than the loss in the standard SO8 package. The conduction loss affected by the package temperature under the conditions of V_{IN} = 19 V, V_{OUT} = 1.3 V, f_{SW} = 500 kHz and I_{LOAD} = 43 A can be calculated as follows:
The measured total losses in the standard SO8 is:
P_{LOSStotalSO8} = 12.71389 W (Eq. 1)
The conduction loss of the low side in the SO8 can be calculated as:
The measured total losses in the PowerPAK SO8 is:
P_{LOSStotalPowerPAK}=12.25391 W (Eq. 3)
The conduction loss of the low side in the PowerPAK SO8 is:
Now, the totalloss deviations caused by the package difference between the standard SO8 and PowerPAK SO8 is:
(Eq. 1)  (Eq. 3) = 0.45998 W
(Eq. 5)
The conductionloss deviations caused by the package difference is:
(Eq. 2)  (Eq. 4) = 0.055 W
(Eq. 6)
Now we can calculate how much conduction loss contributes to the totalloss deviations between the two packages:
Therefore, the difference between the lowside conduction loss in the PowerPAK SO8 and the standard SO8 is 12% of the difference between the total losses for each package type. It is assumed that the remaining 88% is due to dynamic losses caused by package parasitic inductance and thermally shifted threshold voltages.
Package Parasitic Inductance Loss
As stated previously, the PowerPAK SO8 has a package parasitic inductance of 0.3 nH at 100 kHz, while the standard SO8 has 2.12 nH at 100 kHz. The package parasitic inductance increases switching time, resulting in greater switching losses in the SO8 compared to the PowerPAK SO8. The switching waveforms in Fig. 7 show that, as expected, the use of the PowerPAK SO8 package results in a lower peak voltage and less ringing, having 14 cycles compared to 15 cycles in the standard SO8 package.
Another aspect of device packaging that must be taken into consideration is the impact thermal characteristics will have on the MOSFET V_{TH}. When V_{TH} decreases, the MOSFET switching speed increases, resulting in reduced switching loss. From Figs. 6, 7 and 8, the V_{TH} of the lowside MOSFET is decreased by 0.35 at 74°C and by 0.5 V at 84°C, where the conditions are V_{IN} = 12 V, V_{OUT} = 1.3 V, f_{SW} = 500 kHz and I_{LOAD}= 43 A. For the highside MOSFET, V_{TH} is decreased by 0.25 V at 74°C and by 0.35 V at 84°C.
Assuming that all capacitance values remain constant over temperature, the dynamic losses caused by the package parasitic inductance and thermally induced shifts in VTH have the greatest impact on the converter's efficiency.
The End Result
Efficiency for a given package is mainly a function of the package parasitic inductance losses, V_{TH} change and how package thermal properties affect the lowside MOSFET conduction losses. The conduction loss caused by thermal increases to R_{DS(ON)} in the lowside MOSFET is a major factor that contributes 12% of the difference between the respective total losses in these packages. The remaining 88% of the difference between the two package types is mainly from the difference in thermal changes in VTH and parasitic inductance, which is responsible for the observed ringing and peak voltages. Overall, the PowerPAK SO8 shows a 0.8% greater efficiency over the standard SO8 package.
References

Pavier, Mark, et al. “High Frequency DCDC Power Conversion: The Influence of Package Parasitics,” IEEE APEC 2003.

Xiao, Y., et al. “Analytical Modeling and Experimental Evaluation of Interconnect Parasitic Inductance on MOSFET Switching Characteristics,” IEEE APEC 2004.

Cronje, W.A.; Van Wyk, J.D.; and Van Wyk, J.D., Jr. “A Systematic Approach to Modeling of Layout Parasitics in Converter — Initial Formulation,” Proc. of IEEE Power Electronics Specialist Conference 1998, pp. 19441950, 1998.

Ejury, J., and Elbanhawy, A. “Investigations of the Influence of PCB Layout Parasitic Inductances in DCDC Converters on the Efficiency,” International PCIM Europe Conference 2004, pp. 3136.

Nobauer, G., Ahlers, D., and SevillanoRuiz, J. “A Method to Determine Parasitic Inductances in Buck Converter Topologies,” International PCIM Europe Conference 2004, pp. 3741.
SO8  Part Number  R_{G} (Ω)  C_{ISS} (F) at 15 V  C_{RSS} (F) at 15 V  V_{TH1} (V)  R_{DS(ON)} (Ω) at 10 V  R_{DS(ON)} (Ω) at 4.5 V 

Low side  Si4336DY  1.33  5.40E09  4.02E10  2.16E+00  2.30E03  2.95E03 
Si4336DY  1.29  5.51E09  4.08E10  2.23E+00  2.27E03  3.05E03  
Si4336DY  1.31  5.42E09  3.90E10  2.19E+00  2.30E03  2.98E03  
Si4336DY  1.33  5.47E09  3.68E10  2.15E+00  2.40E03  3.02E03  
High side  Si4390DY  0.97  1.49E09  8.98E11  1.53E+00  6.98E03  9.68E03 
Si4390DY  0.97  1.50E09  9.08E11  1.59E+00  6.98E03  9.68E03  
Si4390DY  0.93  1.52E09  9.00E11  1.64E+00  6.98E03  9.83E03  
Si4390DY  0.92  1.53E09  9.06E11  1.72E+00  6.98E03  9.83E03  
Si4390DY  0.92  1.53E09  9.05E11  1.62E+00  6.91E03  9.68E03 
PowerPAK SO8  Part Number  R_{G} (Ω)  C_{ISS} (F) at 15 V  C_{RSS} (F) at 15 V  V_{TH1} (V)  R_{DS(ON)} (Ω) at 10 V  R_{DS(ON)} at (Ω) 4.5 V 

Low side  Si7336DP  1.30  5.49E09  3.88E10  2.21E+00  2.10E03  2.91E03 
Si7336DP  1.29  5.48E09  3.96E10  2.18E+00  2.21E03  2.91E03  
Si7336DP  1.30  5.48E09  3.85E10  2.16E+00  2.26E03  2.93E03  
Si7336DP  1.28  5.54E09  3.85E10  2.16E+00  2.22E03  2.93E03  
High side  Si7390DP  0.96  1.48E09  8.96E11  1.67E+00  6.75E03  9.66E03 
Si7390DP  0.95  1.48E09  9.02E11  1.67E+00  6.72E03  9.60E03  
Si7390DP  0.96  1.50E09  8.97E11  1.57E+00  6.75E03  9.54E03  
Si7390DP  0.96  1.49E09  8.82E11  1.60E+00  7.04E03  9.94E03 
Table. MOSFET data used for the selected devices.