Power Electronics

Optocouplers Support High Power, High Speed Switching Inverters

Gates of insulated gate bipolar transistors (IGBTs) must be driven with stable on and off drive voltages and with relatively high current levels to allow rapid switching between their on and off condition. In addition to allowing rapid switching, high drive current also is a requirement to switch larger power ratings of IGBTs.

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To realize the importance of high-current gate driver circuit design to inverter application, we look to the end equipment design specification, IGBT gate charge, gate capacitance, gate voltage and switching frequency.

Input capacitance is often used as a reference point to design the gate drive circuit. The IGBT datasheet input capacitance, CIES ranges from a few hundred picofarads to hundreds of nanofarads. CIES is the sum of the gate to collector capacitance (CGC) and the gate to emitter capacitance (CGE) as both of them are parallel in circuit configuration (Fig. 1). This IGBT capacitance changes significantly with respect to the collector voltage. This collector voltage variation and Miller capacitance increases the input capacitances value by three to five times larger than the value of the C IES in the IGBT datasheet. Because of this difference, the gate drive circuit design based on datasheet input capacitance is usually inadequate.

The design of the gate driver circuit is calculated more appropriately using the gate charge specified in the datasheet. In Fig. 2, Q GE is the charge from origin point to the Miller plateau region or within time t0. QGC is the charge during t1, which is known as the Miller charge region (plateau). QG is the total charge required to turn on the IGBT, where VGE is the gate drive voltage. QG usually is described in the IGBT manufacturer's datasheet.

The peak current of the gate drive and the average power required for the IGBT can be calculated as follows:

Pavg = VGE × QG × fs


QG = Total IGBT gate charge

fS = IGBT switching frequency (Fig. 2).

The gate charge sequence can be split into three time intervals, t0, t1 and t2. The effective gate capacitance and peak current during each time interval can be computed using the following formula:
QX = IG,X × tX


Where x = 0, 1 or 2 representing the time intervals

The average effective gate capacitance over the gate voltage can be determined from Fig. 2. This average capacitance doesn't “truly” represent the gate driver load. This can be explained by the plateau (interval t1 or Miller plateau region) in the gate voltage waveform, where the voltage is almost constant while the charge is still being induced. This shows interval t1 has a high gate capacitance value. Thus, high peak current is needed to surpass the high gate capacitance during interval t1 or else the IGBT turn-on time will be slow (Eqs. 3 and 4). Because of this high capacitance in the Miller plateau region, high peak current is important — especially for high-frequency switching applications. Likewise, fast IGBT turn-off requires high discharge or sinking current of the gate driver.

In applications using large rating IGBTs, the peak current is the limiting factor to the switching speed. In parallel IGBT applications, a high-current single gate driver can be used to share the driving capability and reduce component count. Typically, a gate driver with 2.5-A peak output can drive IGBTs with ratings up to 1,200 V and 100 A, and drivers with 5-A peak output current can drive IGBTs with ratings up to 1,200 V and 200 A. This rating requirement varies, depending on the switching frequency requirement and ambient temperature.

For very large IGBTs, a noninverting current buffer can be used to boost the IGBT gate drive current (Fig. 3). These booster Q 1 and Q2 transistors have high current capability and large current gain. Place the current buffer as close as possible in the design layout to the IGBT to minimize the parasitic inductance of the gate charging and discharging current loop. The gate resistor, RG to control the peak current to the IGBT, is placed after the buffer circuit.

To charge and discharge the IGBT gate capacitance quickly, the gate driver circuitry should have low impedance. Together with a low impedance path and high output gate current, high-speed IGBT switching is achievable. However, high speed switching creates a new problem. The high speed switching of power semiconductor devices will create a high dV/dt that emits electromagnetic interference (EMI), which can cause erroneous input signals to the gate driver IC and thus result in the end application failing. To prevent this situation, designers often adjust the on and off gate resistances (Fig. 4) by increasing the value. This gate resistance increase, in turn, will delay both the turn-on and turn-off time, which trades off the high switching application design requirement.

In this situation, a gate drive optocoupler can be helpful because it is designed to provide a high common-mode rejection (CMR) against EMI and other noise interferences. Input LED and output to the IGBT grounds are separated from each other, and the internal LED shielding construction provide the needed noise defense (Fig. 5).

The ideal IGBT gate driver IC consists of high speed switching, high peak current capability and high noise immunity. As shown in Fig. 2, the high speed switching brings the gate voltage to the Miller plateau. At the plateau region, the gate drive voltage is fairly constant, and the gate drive IC is required to deliver high current to quickly charge the Miller capacitance. Once past the plateau region, the driver IC will continue to deliver the remaining charges to complete the gate driver cycle.

For high-speed switching applications, EMI generation is an issue and could create erroneous switching operation that may lead to application breakdown. Gate drive optocouplers with high current output and high CMR are a good solution, as they provide noise immunity and high current drive capability for large IGBT and fast IGBT switching applications.

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