Power Electronics

The ESDA and JEDEC Revise Standards for ESD Testing

JEDEC Solid State Technology Association and the ESD Association today announced the publication of ANSI/ESDA/JEDEC JS-001-2011 for Electrostatic Discharge Sensitivity (ESD) Testing - Human Body Model (HBM) - Component Level. The product of a ESDA /JEDEC agreement to produce joint standards in the field of device ESD sensitivity testing, the new revision represents a significant update over the prior version of the standard. ANSI/ESDA/JEDEC JS-001-2011 may be downloaded free of charge at www.ESDA.org or

The new ANSI/ESDA/JEDEC JS-001-2011 revision incorporates several important updates; they include a significant modification in the required pin combinations which will greatly reduce test times, increase productivity, reduce costs, and minimize false failures. These changes include:

  • Most non-supply to non-supply (I/O-to-I/O) eliminated - testing is limited to differential pairs
  • Eliminated "cross-domain" testing of non-supply (I/O) pins
  • Pin combinations for two-pin testing clarified
  • Use of "single polarity" supply-to-supply stressing allowed

The primary changes are described in a new pin combination table (Table 2A). The older set of combinations are still permitted and summarized in Table 2B. An expanded annex provides further guidance to allow the user to minimize the interaction between the HBM tester parasitics and the device under tests. This will allow for more accurate HBM tests.

The prior version of the new standard (JS-001-2010) merged two previously existing, similar test methods developed by ESDA and JEDEC, with the goal of establishing a unified procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). ESD can significantly impair the reliability and operation of solid state devices, and test methodologies are becoming ever more critical to the industry as technology advances and device complexity increases.

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