As advanced logic chips move to feature sizes of 65 nm and below, the increase in leakage current threatens to derail mobile IC designs, which have power budgets that are severely limited by battery capacity. To counter this problem, Texas Instruments has developed a set of power management techniques—collectively known as the SmartReflex Technologies—which the company introduced this week at the Portable Power 2005 Conference in San Francisco. These adaptive power management techniques dramatically limit leakage current and leakage power, while also tightly controlling power consumption in the chip’s active-mode operation.
SmartReflex represents a combination of intelligent and adaptive silicon, circuit design and software that can be deployed in ARM processors, digital signal processors, graphics accelerators and other high-speed CMOS devices developed in next-generation processes. Although many of the techniques that constitute SmartReflex have been used previously, the combination of so many of these techniques and the extent to which they may be implemented dynamically is said to be unique to SmartReflex. And beyond invoking power management within the processor, SmartReflex also invokes control of the mobile device’s power supply chip, which must be programmable.
Using a technique called static leakage management (SLM), SmartReflex can reduce a processor’s quiescent current in standby by a factor of 40. SLM essentially shuts off power to the chip except for retention memories, which sit in parallel with the main logic and main memories. Because the retention memories operate at a higher threshold voltage than other on-chip memory, they exhibit much lower levels of leakage current. Although the higher threshold voltage slows access to these memories, that limitation is not a factor because they are being used just for backup. Moreover, the contents of the retention memories can be quickly loaded into the chip’s regular memories.
Adaptive voltage scaling, dynamic voltage/frequency scaling and dynamic power switching are a few of the other techniques that SmartReflex applies. The first two techniques reduce active mode power consumption by reducing either the core supply voltage or clock speed. Since a chip’s active-mode power draw is a function of CV²f, reducing either supply voltage (V) or clock frequency (f) will reduce power consumption.
Adaptive voltage scaling (AVS) adjusts the core supply voltage based on “process strength” and the chip’s internal operating temperature. Process strength refers to the variation in chip performance versus supply voltage that results from wafer to wafer variations. At the same time, chip performance also varies with temperature. In adjusting core voltage as a function of process strength and operating temperature, the goal is to obtain the desired chip performance at the minimum possible supply voltage.
Similarly, with dynamic voltage/frequency scaling (DVFS), the processor determines what level of performance (clock speed) it requires to carry out its current operations, and adjusts both clock speed and supply voltage for the minimum necessary values. DVFS involves a continuous optimization of the core voltage; therefore, it demands fast communications with the IC that supplies power to the processor. SmartReflex relies on a fast I²C interface for this purpose. Dynamic power switching (DPS) shuts down different functions within the processor when they are not in use, switching between high- and low-power modes of operation.
The OMP2420 application processor, which the company announced last year and is now entering production, employs certain SmartReflex techniques. Although this part is built in a 90-nm CMOS process, where leakage is less of a concern than at 65 nm, the OMP2420 demonstrates the capabilities of SmartReflex, particularly the 40X reduction in leakage current, which will become a critical asset in next-generation chips. The company will offer SmartReflex as a toolkit for ASIC and standard products. For more information, see www.ti.com/wirelesspressroom.