In Shootout Volume 4  , isolated brick converters were considered with a particular focus on eighth-brick converters where size constraints are most severe. These isolated brick converters are widely used in telecommunication systems to provide operating power to network equipment and are available in various standard sizes, input and output voltage ranges. Their modularity, power density, reliability, and versatility has simplified, and to some extent commoditized the isolated power supply market. What they all have in common is that the input and output power devices are all rated at 100 V or lower. There are, however, isolated converter applications with higher device voltage requirements, such as the PoE - PSE (Power-over-Ethernet Power Sourcing Equipment). These converters benefit even more from the advantages that eGaN FETs brings with increasing voltage rating. In this article, an eGaN FET based half-brick converter is constructed and compared to a similar SoA (state-of-the-art) silicon MOSFET brick converter.
Development of the Power-over-Ethernet (PoE) standard has been evolving over the last few years. The main focus seems to have been power level and the systematic increase of power with each new class and type. According to the IEEE 802.3at standard on PoE , the PSE requires an output voltage between 44 V and 57 V for PoE type 1 and between 50 V and 57 V for PoE type 2 (PoE+). It also has to be capable of delivering 15.4W (type 1) or 25.5W (type 2) per port on the PSE Ethernet switch. For the PSE, the output requires some form of regulation, but tight regulation is not required. It is interesting to note that there is an increase in minimum voltage to account for the increase in maximum line droop with the increased power level ñ future PSE equipment may require even smaller voltage ranges closer to the 57V maximum. With 24, 36 or even 48 ports per Ethernet switch typical, the total PSE supply power required can be as high as 1.2kW. This drives the need for higher efficiency and higher power density converters.
As these brick converters are of a strictly defined size, designers are forever coming up with innovative ideas to increase their output power (and power density). Although these ideas are numerous and varied, they are all related to system efficiency. This is a physical limit based on the fixed volume of the converter and the method of heat extraction. For a half-brick converter, it is difficult to remove more than 35 W of losses, even with significant airflow and/or base plate.
In Fig. 1, the resultant output power that is achievable in a half-brick is plotted versus the required minimum full load efficiency to achieve this. Since most commercial half-brick PSE converters already have about 95% efficiency; even a half-percent efficiency improvement is important and can increase output power by an additional 100 W or so. Cost per watt ($/W), however, is the most important aspect. Increasing brick efficiency, and therefore output power, reduces the overall cost of the module per watt.
Isolated Converter Comprison
When trying to compare half-brick PoE - PSE converters, it becomes impossible to perform a straightforward apples-to-apples comparison, as there are a significant number of variations between commercial designs. With each generation of power supply, an increase in output power level is achieved as each manufacturer interprets their “optimum” design in terms of structure, layout and topology changes differently. Determining the “best” solution is an iterative process, which may further be complicated by differences in opinions as to what exactly the “best” solution is. A great example of this diversity in designs for this half-brick application is whether to build two interleaved converters or to build a single converter. Furthermore, the use of either single-stage conversion or two-stage conversion approaches are both utilized in current commercial products.
For larger brick sizes, such as the half-brick, the resultant output power levels and overall converter losses are high enough that multiple power devices are usually required for each switch -- both from a thermal requirement as well as from a minimum available RDS(ON) (largest die size) perspective. Thus, if the converter were to be split into two converters -- each for half the power -- the overall power device count would not be affected. The added cost and size of using an increased number of inductors and transformers is also questionable, as these components would be smaller and interleaving of the power converters would allow a reduction in the required output capacitance. Furthermore, the size and especially height restrictions of the bricks mean that a single high power transformer would be height -limited with a less optimal magnetic path-length than two smaller transformer cores. The remaining differences, gate drive and control, are likely the determining factors -- i.e. can their cost increase be justified through better efficiency and therefore increased output power?
As with the eighth-brick in Shootout Volume 4 , an eGaN FET-based converter was developed that is not necessarily a universally optimal solution. The design goal was to deliberately push the operating frequency much higher than current commercial systems to show that eGaN devices could enable someone skilled in power supply design to develop state-of-the-art next-generation products with increased efficiency and output power.
Prototype PSE Converter
For the 48 V to 53 V eGaN FET based half-brick PSE converter, a phase-shifted full-bridge (PSFB) converter with a full bridge synchronous rectifier (FBSR) topology was chosen as shown in Fig. 2.
Because of the high power level, two interleaved converters are constructed within the half-brick footprint, rather than one converter with parallel devices. Not only does this avoid any of the complexity associated with paralleling devices , the use of two separate converters conceptually allow for phase shedding to improve light load efficiency.
Efficiency results for one and two phase operation are shown in Fig. 3 where light load efficiency is improved by at least 2% with simple phase-shedding. Each converter operates at 250 kHz device switching frequency resulting in an output ripple frequency of 1 MHz. A more complete schematic is shown in Fig. 4.
The aim was to show that with the increase in switching frequency and relatively small eGaN FET device size, two of these converters can be constructed within the available volume constraints. The choice of transformer turns ratio (4:7) meant that, at 60 VIN, the secondary side winding voltage (not including switching spike) would be about 105 V and therefore 200 V devices were used on the secondary side with 100 V devices on the primary side. The actual eGaN FET-based prototype is shown in Fig. 5. It shows that, unlike conventional brick designs, the magnetic components are not integrated within the main printed circuit board (PCB), but are separate PCBs for the transformers. Not only does this reduce the number of layers required for the main PCB, but it also allows the use of conventional surface mount inductors for the output filters. The converter was constructed using an 8 layer, 2 oz copper per layer, printed circuit board. The transformer windings are created by laminating two 8 layer PCBs together (in parallel) within the winding window.
PSE Converter Shoot-out
The eGaN FET-based prototype half-brick PSE converter can be compared against similar 48 V to (approximately) 53 V fully regulated commercial half-brick converters. As stated previously, these commercial converters span a range of topologies and configurations as listed in Table 1.
To emphasize how the eGaN FET-based prototype compares to these converters, two products (B and D in table 1) have been selected to highlight the overall results.
Converter D is a conventional single single-stage, single-transformer converter with a similar topology to the prototype (although the eGaN FET prototype has two parallel converters).
The efficiency comparison in Fig. 6 and Fig. 7 shows the light load efficiency advantage that is possible with slower switching frequency and possible light load optimization through careful design of the core losses and leakage inductance. By comparison, in the eGaN FET prototype, the core was designed only to minimize leakage inductance and deliberately switch at 75% higher switching frequency. Thus, although light load efficiency was lower, by about 50% load this was no longer the case and the eGaN FET prototype eventually produced 25% more power at full load for a similar total converter loss (Fig. 6 shows loss comparison).
The second commercial half-brick (Converter B) used for comparison, has a two-stage approach. Although the two-stage approach is different than our prototype approach, both have the output power split into two separate converters operating in parallel. The advantages of the two-stage approach are that it allows efficiency optimization of the unregulated isolation stage since it operates at fixed duty cycle and voltage regardless of converter input voltage and, this controlled input and output voltage allow the use of lower voltage rated devices with better figures of merit (FOMs). The disadvantage is the additional conduction losses for two stages and the increased complexity and component count. Fig. 8 shows the efficiency comparison between the eGaN FET prototype and the two-stage converter. This shows the optimization process that has gone into this product as the peak efficiency is achieved at the nominal input of 48 V. The differences in topology can best be described by comparing the 38 V (low line) input voltage results: Since the two-stage circuit employs a boost regulation stage, low line voltage is actually the worse case conditions (conduction loss increased, with no appreciable reduction in switching loss), while for the traditional single stage approach, low line is the best case, as switching loss is minimized. With the two-stage approach, power losses at low line reach almost 50 W (almost double that of the eGaN FET prototype under the same conditions), as shown in Fig. 9, while the 75 V (high line) input losses are very respectable -- only 15 % higher than the eGaN FET prototype but operating at 25% higher voltage.
It is important to note that the choice of topology and component optimization is as important in brick converter design as the selection of the best power devices. A skilled design engineer should be able to further improve the eGaN FET prototype results presented here.
- Johan Strydom, Andrew Ferencz, ìeGaN® FET-Silicon Power Shootout Vol. 4: Brick Convertersî Power Electronics Technology, July 2011, http://powerelectronics.com/discrete-semis/silicon-power-shootout-brick-converters-0711/
- IEEE 802.3atTM-2009 ethernet standard, http://standards.ieee.org/about/get/802/802.3.html
- Micahel de Rooij, Johan Strydom, ìeGaN® FET-Silicon Power Shootout Vol. 5: Paralleling eGaN® FETs -- part 1-- http://powerelectronics.com/power_semiconductors/gan_transistors/paralleling-egain-fets-part1-0911/index.html