Power density, space and system efficiency are the principal goals in design of power supplies for portable computer, motherboard, server, gaming, telecom, POL and DC/DC brick applications. With efficiency exceeding 90%, the synchronous buck converter has emerged as the preferred solution for power supplies used in these systems. To further boost efficiency while refining designs for smallest possible size, engineers look to integrate discrete devices and optimize component selection.
The circuit design for a synchronous converter typically includes both a high-side (control switch) and low-side (synchronous rectifier) MOSFET. Compared to basic buck converter designs, the low-side device replaces a rectifier diode, resulting in a significant efficiency gain by reducing heat dissipation in the OFF state. One effect of replacing the rectifier diode is that the supply operates in continuous current mode, which can lower efficiency in systems that frequently run at light duty loads. Thus, depending on design goals, the synchronous rectifier MOSFET may be coupled with a Schottky-like diode to limit power loss incurred during the OFF state transitions of the switching cycle.
To address both integration and optimization, devices that integrate both the high-side and low-side MOSFET into a small single package are now available. These are implemented as an asymmetric half bridge (Fig. 1). With the internal connection of high-side and low-side MOSFETs, the designer can achieve low parasitic loop inductance in a compact and simplified layout for a DC/DC converter, thus reducing footprint area by 50% or more compared to a design based on discrete MOSFETs.
A family of PowerStage products implement this approach for buck converter designs. Based on Infineon’s low RDS(ON) 25/30V OptiMOS™ technology, the devices provide DC/DC conversion efficiency up to 93.5% in applications ranging from 0A to >30A.
Basic DC/DC Buck Converters
The semiconductors of the buck converter are a switch (usually a power MOSFET) and a rectifier. The latter device is designed as synchronous rectifier to minimize conduction loss during the freewheeling phase. A MOSFET as the synchronous rectifier is operated in reverse, utilizing the body diode of the MOSFET as commutation element during the dead time.
Together with the input MLC (multilayer ceramic capacitor) decoupling capacitor, these two MOSFETs form a current commutation loop which mainly defines the transition speed and dynamic loss of the buck converter. The goal of a good design is to minimize the stray inductance in this commutation loop by proper layout and device selection. In line with the general trend in package size reduction, the MOSFETs used in typical synchronous buck converters have shifted from big leaded packages such as DPAK and D2PAK to the much smaller SSO8 (5mm x 6mm) and S3O8 (3mm x 3mm).
Integrated Control Switch
With the integration of both the control-FET and the synchronous rectifier FET into one common package, all of the device interconnects are also implemented within the package. This helps to reduce stray inductance and hence lowers dynamic loss. The devices can also incorporate a Schottky-like diode monolithically integrated with the synchronous rectifier FET. Applications requiring 0A to 10A are accommodated in PowerStage3x3, while applications requiring 10A to over 30A will utilize PowerStage5x6 (including integrated Schottky-like diode versions).
The PowerStage devices are implemented as chip-by-chip assemblies. This way, every chip is directly connected to the leadframe and can be cooled into the board. The PCB temperature is reference for both MOSFETs. The particular layout of a power supply can be varied to optimize for cooling, space constraints (e.g. routing in inner planes), or efficiency. To illustrate space savings, Fig. 2 shows a possible component arrangement of a single phase in a multi-phase DC/DC-buck converter.
Available evaluation boards for both the PowerStage3x3 (Fig. 3) and PowerStage5x6 (Fig. 5) devices serve to illustrate opportunities for changing the operating parameters while maintaining high efficiency in a small space. In the tests reviewed here, the phase node has not been used as a cooling area and the performance results from the implemented silicon technology itself. The boards are implemented with four layers of 2 oz. copper per layer. This demonstrates that the achieved performance can be obtained with very little requirements on PCB and routing.
The efficiency of the two 3x3 devices is illustrated in Fig. 4, under the given operating conditions it runs at up to 10A. Next, the efficiency of the 5x6 device with the lowest Ohmic performance (BSC0911ND) is illustrated in Fig. 6.
The main cooling path for PowerStage devices is into the PCB. Big pads of VIN and Phase support the direct heat transfer from the MOSFET dies into the board. The performance can vary depending on the inductor’s location, copper thickness, and thermal vias. Fig. 7 provides insight into the thermal characteristics of the PowerStage5x6 device in the very small cooling areas of the evaluation board. The thermal resistance RthJA for the board without airflow is 19 K/W.The PowerStage3x3 can operate up to 10A under the conditions given. Since the evaluation board is small (4cm x 4cm) the reference temperature of the board also increases quickly. Fig. 8 shows that the PCB itself has a temperature in the vicinity of 100°C. Cooling with even a slight airflow can effectively help to operate the device at 100°C.