An improved SPICE model has been developed by Fairchild engineers for the simulation of trench power devices using the BSIM3 MOSFET model. The new model architecture seeks to eliminate shortcomings in the level 1 and level 3 subcircuit methods used extensively for modeling MOSFETs in power circuits. The new model offers excellent correlation to product data, transistor scaling not possible with other power MOSFET models, robust simulation and reduced simulation time.
Level 1 Subcircuit Model
The level 1 SPICE MOSFET model is the simplest and most basic of all models. Semiconductor manufacturers have used it widely for the simulation of power MOSFET devices. But because of its simplicity, it does have limitations. Among them is a lack of voltage-dependent capacitance. This will limit the model's ability to accurately simulate switching events.
Poor simulation of conduction in the subthreshold region is another limitation of the level 1 model, so linear-mode circuits may have discontinuous transitions from one gate-drive condition to another. To overcome these limitations, an elaborate subcircuit model was developed providing for voltage-dependant capacitance, subthreshold conduction, breakdown voltage and body-diode forward conduction (Fig. 1).
While the circuit shown can accurately model a power MOSFET, it occasionally has convergence errors and the simulation time is relatively long. This model is implemented with no process or physical properties related to the device; thus, it is not easily scaled for new die sizes.
A typical example of a level 3 subcircuit model was published by Motorola in 1989. This approach has a single MOSFET for dc characterization and two controlled switches to model the variation of capacitance with applied voltage. Although it's an improvement over the level 1 MOSFET model, the level 3 model also has weaknesses in the subthreshold region and lacks voltage-dependent capacitances. The controlled switches enable the subcircuit model to simulate the voltage-dependent capacitances.
BSIM3 SPICE MOSFET Model
From inception, device models in SPICE were designed to be scaled, thus enabling chip-level modeling of circuits comprised of different size transistors. The process features — such as gate-oxide thickness, channel length and channel-doping concentration — define the device performance. With all the process features being common, channel width alone would then determine the I-V characteristics of the MOSFET in the simulated IC.
As evidenced by the macro-model approaches discussed previously, power MOSFET suppliers have struggled to represent the I-V and C-V characteristics of this class of device with a simple standard SPICE MOSFET model. Resorting to various methods to enable voltage-dependant capacitance and switching, these models cannot readily take advantage of the transistor-size-scaling capabilities of SPICE and tend to suffer from increased simulation time and convergence errors.
In this work, every effort has been made to overcome the scaling limitations of the previous model configurations, while at the same time providing excellent I-V and C-V correlation to characterization data. At the time of this writing, only trench-gate MOSFET structures have been built using the model described here. Planar-gate vertical double-diffused MOSFET (VDMOS) power devices have the additional complication of a parasitic JFET-like structure in the drift region current path, which may complicate the application of this simplified model.
It turns out to be relatively easy to define trench-gate VDMOS device features analogous to the architectural elements of the basic MOSFET structure on which the BSIM3 MOSFET model is based. When a representative half-cell cross section is rotated to show the gate in a horizontal direction more recognizable to those familiar with CMOS devices, the source, drain, gate and substrate (body) elements can more easily be related to their lateral MOSFET counterparts (Fig. 2). The magenta elements are conductors, so it should be clear that the source and the source-substrate contacts occur along the left vertical edge of the drawing, while the drain contact (not shown) would be on the right vertical edge.
With the trench MOSFET device features now mapped to equivalent lateral MOSFET structures, specific BSIM3 MOSFET model parameters can be determined for both I-V and C-V equations in SPICE. While outside the scope of this work, the BSIM3 MOSFET model parameters are defined and explained in great detail in other references. By way of example, the BSIM3 parameter representing the overlap area between the source and the gate (CGSO) can be determined from the process and by device and process simulation. Similarly, the other BSIM3 MOSFET model parameters can be determined from the process and device features.
Having defined the trench MOSFET model only by parameters based on process and device features, the scalability of the device model in SPICE is restored. While it is beyond the scope of this overview, because the model parameters are based entirely on process and device features, knowing the process variation of those features enables the application of Monte Carlo circuit variability simulations. The restored scalability of the device model also allows product definition studies for sizing of the trench power MOSFET for optimum performance in the power application circuit.
One aspect the BSIM3 MOSFET model does not simulate is the breakdown voltage that is enabled in our model by subcircuit components EBREAK, DBREAK, RBREAK and IT (Fig. 3). The voltage-controlled voltage source, EBREAK, when coupled with RBREAK and IT, determines low current avalanche breakdown voltage. The thermal compensation elements, TC1 and TC2, of RBREAK correct the temperature dependence of the low current breakdown. High current breakdown and the associated temperature dependence are accounted for by the series resistance and thermal coefficients of DBREAK.
The resistor RDRAIN corrects for the nonsilicon temperature-dependant effects on drain-source resistance. Without RDRAIN, the on-resistance dependence on temperature would be linear as opposed to an increasing ratio with temperature.
Other elements have been included in the subcircuit model to improve the accuracy of the switching simulation. RGATE is a lumped representation of the distributed gate resistance, while LDRAIN, RLDRAIN, LSOURCE, RLSOURCE, LGATE and RLGATE account for the package parasitic impedances.
The BSIM3 MOSFET model does not provide for any direct connection between the gate and the source terminals. As a result, there is no leakage current from the gate to the source. The gate leakage current can be modeled by adding a large-value resistor between the gate and source, but is not included in our subcircuit model.
With a few minor exceptions, remarkable agreement has been demonstrated when product characterization and simulated MOSFET behavior are compared. For example, Fig. 4, Fig. 5, Fig. 6, and Fig. 7 plot simulated results versus measured data for the FDB8441, a 40-V n-channel trench MOSFET. In this case, the transfer characteristics curve shows only inconsequential deviation from the data in the weak inversion and subthreshold regions when simulated at high temperature. This is due to a discrepancy in the drain-source leakage current at the elevated temperature condition for which the BSIM3 MOSFET model does not account.
The capacitance simulation also reveals a difference in CRSS compared to product data (Fig. 7). On the other hand, the gate charge simulation does accurately represent the product data. When used to simulate a dc-dc switching converter application, the model produced comparable switching characteristics to the application waveforms.
Use of SPICE Model
Using a standard MOSFET symbol makes for a quick and simple way to simulate various MOSFET SPICE models. There are symbol files on the Fairchild website for use with the OrCAD Capture and Schematic tools. The symbol for a standard three-terminal MOSFET is shown in Fig. 8 and can be accessed at www.fairchildsemi.com.
The symbol file should be downloaded and saved in the directory where modeled library files are located. From an open schematic, select the icon or menu item to place a new part. The “Place Part” window is shown in Fig. 9.
In this window, select “Add Library.” Browse for and open the symbol file that was downloaded and saved to the working directory. From this new library, select the symbol “Fairchild MOS Std” and place it into the schematic. Once the MOSFET symbol has been placed, the model name will need to be changed. Double click on “Fairchild MOSFET” on the symbol just placed and enter the model name to be simulated. The final step is to add the library to the simulation profile. Within the “Capture” window, open a simulation profile and select the “Configuration Files” tab and category “Library.” Browse to locate the library file containing the model to be simulated. Next select the “Add to Design” button to make the model ready for simulation.
If a different model is to be used at a later point in time, not all of these steps are required. From the schematic, simply change the name of the MOSFET model. Then add the library file to the simulation profile if it has not been previously added.
Alternatively, a library can be added globally to “Capture.” When adding the library file to the simulation profile, select the “Add as Global” button. This library file will then be available for all designs in “Capture.”
We have demonstrated a greatly simplified, exceptionally accurate trench power MOSFET model using a single BSIM3 device at its root. The resulting model can easily be scaled to simplify model development and can enable performance variation simulation. These new models are available for download from the Fairchild Semiconductor website at http://webdc.transim.com/fairchild/index.html.
Cordonnier, C. E.; Rossel, P.; Maimouni, R.; Tranduc, H.; Allain, D.; and Napieralskadouard, M., “Spice Model for TMOS Power MOSFETs,” Motorola Semiconductor, AN1043/D, 1989. www.onsemi.com/pub/Collateral/AN1043-D.PDF.
Liu, William, “MOSFET Models for SPICE Simulation including BSIM3v3 and BSIM4,” John Wiley & Sons Inc., 2001. Chapter 3, pp. 103-104.