Most common electronic devices require an input voltage source to operate. The voltage source may be a battery for portable devices, an AC line source for consumer electronics, or even a regulated DC voltage bus for industrial or telecommunication applications. This input voltage source needs to be converted to a lower voltage, since individual circuits such as processors, memory, field programmable gate arrays (FPGAs), etc., require a much lower voltage to operate. Typically, buck converters are used to step down the input voltage source to the required voltage. In some cases, generating a negative voltage from a positive input voltage source is required. These applications can include double-ended sensors, audio amplifiers, line drivers and receivers, or instrumentation amplifiers. In such instances, it is possible to configure the step-down converter into an inverting buck-boost topology, where the output voltage is negative with respect to ground.
Using a synchronous topology has certain advantages over a non-synchronous topology, such as higher efficiency at low voltages. The synchronous topology stays in continuous conduction mode (CCM) even at very low currents as opposed to a non-synchronous topology that runs into discontinuous conduction mode (DCM) when the current through the inductor is reduced to zero. The disadvantages of non-synchronous topology in DCM are a slow transient response and the need for a slower control loop for the DCM shift. These disadvantages can be eliminated by using a synchronous topology.
Using a switcher with internal FETs is optimal in applications for small designs since it has both high-side and low-side MOSFETs included in the integrated circuit (IC). Using a device with internal FETs helps to reduce the components required in a board-level design.
A synchronous buck converter consists of two switches and an inductor-capacitor (LC) filter. It operates by applying a pulse-width modulated (PWM) waveform to the LC filter. The PWM waveform is created using two MOSFET switches. The PWM waveform is then averaged out by the LC filter to produce a DC output voltage. The basic buck topology is presented in Fig.1.
The output voltage is calculated using the input voltage and the duty cycle (duty cycle is defined as the ON time of high-side FET over the total period of time, for continuous conduction mode) as show in Equation (1). The steady-state load current is carried by the inductor during the whole time period. During the ON time of the high-side FET, the voltage across the inductor is the input voltage less the output voltage and the inductor stores current at the rate depicted by Equation (2). During the OFF time of the high-side FET, the voltage across the inductor is reversed and equal to the output voltage and the inductor discharges current at the rate depicted by Equation (3) with a negative ramp.
INVERTING BUCK-BOOST TOPOLOGY
An inverting buck-boost converter consists of two switches: an inductor and a capacitor similar to a buck converter. But the output voltage and ground test points are reversed in order to achieve a negative output voltage. The basic buck-boost topology is presented in Fig. 2.
The output voltage is calculated using the input voltage and the duty cycle (duty cycle is defined as the ON time of high-side FET over the total period of time, for continuous conduction mode) as shown in Equation (4). During the ON time of the high-side FET, the voltage across the inductor is the input voltage and the inductor stores current at the rate depicted by Equation (5), while the output capacitor provides load current. During the OFF time of the high-side FET, the voltage across the inductor is reversed and equal to negative output voltage and the inductor discharges current at the rate depicted in Equation (6) with a negative ramp. The inductor provides the load current during this phase and also recharges the capacitor.
In order to select a step-down regulator for this concept, it is important to consider a few criteria. To power up the board, the input voltage needs to be higher than the minimum required voltage for the device chosen. The maximum allowable output voltage is limited by the maximum Vdev.
To demonstrate the performance of the inverting buck-boost topology, a test circuit was constructed using the TPS54620 from Texas Instruments, as illustrated in Fig. 2. The test circuit is powered by 5V and produces -5V at 2A. A few waveforms are presented to demonstrate the inverting buck-boost topology. Fig. 3 depicts the switch node swinging between +5V and -5V. Fig. 4 shows the output transients of 11.6 mV when the load current is stepped between 0.5A and 1.5A. Fig. 5 shows the efficiency of the device in buck-boost topology and Fig. 6 shows its stability at full load of 2A.
There are several buck converters such as the TPS54620 that can be used to create an inverting buck-boost converter to produce a negative voltage from a positive input voltage. For a detailed design example using this technique, see Reference 1.
For more information about Switchers with integrated FETs from Texas Instruments, visit: www.ti.com/mosfet-ca.