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High-speed servers, workstations and clock distribution networks are applications that require transistor-transistor logic (TTL) to emitter-coupled logic (ECL) translators. Differential ECL devices typically require both a positive and negative output voltage. When the input power is a positive dc voltage, several methods exist to create the voltage inversion necessary for the negative output voltage.
A charge-pump, inverting buck-boost and Cuk converter are all possible topologies. Each requires a dedicated control circuit for regulation. Except for the charge pump, multiple components, such as an inductor, FET and diode, are needed in each power stage. The inverting charge pump is a more compact solution, but suffers from poor efficiency and voltage regulation as the load is increased.
Flybacks and other transformer design approaches are also candidates. These approaches would only be selected if justified by the need for other high-power output voltages in the system. In such cases, the negative 5-V output would be post-regulated via a linear regulator from a transformer's auxiliary winding. None of the approaches mentioned combine the virtues of low-cost, high-performance and small area. A simple solution described here can address these shortcomings.
The dual synchronous-buck converter in Fig. 1 represents a typical design solution for the positive 5-V output voltage and a second system-defined output voltage, which in this case is 3.3 V. The circuit within the highlighted box identifies the additional components used to generate the negative 5-V output. The positive 5-V circuit operates as a standard synchronous-buck converter, with the switching cycle consisting of two parts.
During the first period of the switching cycle, the top FET Q2A conducts and applies a voltage equal to VIN — VOUT across inductor L1 pins 3-1. FETs Q2B and Q1 are off during this time, and the negative 5-V output capacitor C2 supplies all of the negative 5-V output current. C2 must be sized appropriately to supply the negative 5-V current during this period and keep the negative 5-V output ripple voltage within the required specifications.
While Q1 is off, it must block a voltage equal to the negative 5-V output voltage plus the voltage coupled across the auxiliary winding of L1. With the 1-to-1 turns ratio of L1, the Q1 blocking voltage is essentially equal to the input voltage.
During the second part of the switching cycle, the controller switches the top FET Q2A off and the bottom FET Q2B and Q1 on. The voltage on the inductor L1 pins 1-3 must reverse to maintain current flow in the same direction (into the output). This puts a positive voltage on the “dot” of the coupled inductor winding. The magnitude of the voltage across L1 pins 1-3 is now clamped to a level equal to the output voltage plus the relatively small voltage drop of Q2B.
Note that during the bottom FET Q2B conduction time, current flows in a clockwise direction through the inductor and the load, returning through the bottom FET Q2B and the inductor. During this conduction phase, the coupled inductor secondary winding, pins 2-4, has a voltage equal to the voltage on pins 1-3, since both windings have an equal number of turns. Since FET Q1 is on, current flows from the secondary winding into the load as well as replenishing the charge in C2.
The voltage present at the negative output is equal to the inductor's secondary voltage, minus FET Q1's conduction voltage drop and the inductor's resistive drop. Selecting an inductor with low winding resistance and a FET with low on-resistance will minimize these voltage drops. The result is less variation in the negative 5-V output as its load increases. Minimizing the on-resistance of bottom FET Q2B also improves the voltage regulation on the negative 5-V output because this drop is proportional to the positive 5-V output current.
It's interesting to note that the higher the FET Q2B's voltage drop, the more negative the negative 5-V output becomes. It is possible that the voltage drops of FETs Q2B and Q1 can cancel each other out under certain positive 5-V and negative 5-V output load conditions, resulting in perfect output-voltage matching.
The gate-drive voltage of Q1 is derived from the gate-drive voltage of the bottom FET Q2B, as both FETs operate in-phase with each other. The peak-to-peak amplitude of the bottom FET gate-to-source voltage is 5 V, as set by the controller. Capacitor C1 ac couples this switching signal, but blocks its dc average level. Diode D1 conducts only during a negative voltage swing, clamping Q1's gate voltage to 0.7 V below the source pin and turning it off.
During a positive voltage swing, the peak voltage will now be 5 V greater than when it was off. This gives a positive gate-to-source voltage of approximately 4.3 V, turning Q1 on. The use of a MOSFET with a 2.5-V gate-to-source threshold is necessary to ensure that Q1 becomes fully enhanced. The use of diode D1 allows nearly all the available drive voltage amplitude (less one diode drop) to be used for the positive-going gate-to-source voltage.
Without D1, the positive-going gate-to-source voltage amplitude would vary with duty cycle. Its lowest amplitude is when the input voltage is greatest, and increasing the likelihood that Q1 could not turn on properly. The body diode of Q1 allows the negative 5-V current to conduct through it during the FET switching transition times (and before Q1 fully turns on), but cannot provide the low forward drop necessary for good output regulation. N-channel devices are utilized for Q1, allowing for lower RDS(ON) values than p-channel devices, as well as a much greater selection of commercially available devices.
Fig. 2 shows FET Q1's measured gate voltage obtained with respect to ground along with the negative 5-V output voltage as reference. Resistor R1 and the input capacitance of Q1 provide high-frequency filtering on the waveform edges, while resistor R2 provides a low impedance pull-down to prevent the drive signal from floating.
Fig. 3 shows the currents measured in inductor L1's primary and secondary windings at full load. It can be seen in the positive 5-V inductor current (top) that the current's down-sloping portion must supply the current to both the positive 5-V and negative 5-V outputs simultaneously, as well as replenish the charge in the negative 5-V output capacitor. This results in nearly a 50% increase in the peak-to-peak ripple current in the primary, and necessitates additional output capacitors on the positive 5-V output in order to keep the output-ripple voltage low.
Since the secondary winding current is delivered in pulses, it places a larger burden on the output capacitors for the negative 5 V. It is not hard to see that, with a large negative 5-V load current, the positive 5-V and negative 5-V outputs would require excessively large output capacitors to maintain reasonable ripple voltages. This is why only light loading on the negative output — relative to the positive output — is recommended.
This circuit uses a Coiltronics DRQ127 coupled inductor, which has a very low winding resistance and a high dc current rating. It comes in a standard-sized package that is only slightly larger than a comparable single-winding inductor and with only a marginally higher cost. The best circuit performance is realized with the lowest possible winding resistance, since winding resistance degrades voltage regulation as the load increases.
Output voltage waveforms at powerup are shown in Fig. 4. The negative 5 V is able to track the positive 5 V precisely. This is due to the inductor's secondary-winding voltage being clamped to the positive 5-V output voltage on a pulse-by-pulse basis. Regardless of the positive 5-V output voltage, the negative voltage will track it within the small voltage drops associated with Q2B, Q1 and the winding resistance of L1.
In Fig. 5, measurements on the negative 5-V output reveal its load regulation. The curves highlight the variation in the negative 5-V voltage as it is loaded, with each curve at a different positive 5-V load. There is ±1% variation in voltage regulation over loading and another ±1% variation from cross-loading the positive 5-V output. This results in a total output variation of ±2%. The losses associated with the additional circuit are quite low. The additional output achieves 95% efficiency alone under most loading conditions.