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In part one of this article series, we found that total component stress factors (CSFs) — a new analysis method that enables the comparison of different power conversion topologies — for buck and boost converters were the same for fixedline voltage where the stepdown ratio of the buck converter was equal to the stepup ratio of the boost converter. In this second part, we focus on nonisolated applications with limited linevoltage range.
Buck and boost converters are part of the same canonical cell where the differences between the buck circuit and the boost circuit are the line and load connections. We illustrate this relationship in Fig. 1 where the circuit operates as a buck converter for power flow from left to right and as a boost converter for power flow from right to left.
Instead of treating the stepup and stepdown problems separately, we recognize that a stepup converter is a stepdown converter that operates with power flow reversed. Therefore, any of the circuits in this second part of the article series can be operated either as stepup or stepdown. In every case, power flow from left to right will correspond to stepdown conversion, and power flow from right to left will correspond to stepup conversion.
In part one, we found that the lowest CSFs for the buck converter occurred for stepdown ratios near 1 and that the lowest CSFs for the boost converter occurred for stepup ratios near 1. We will consider the problem where the stepup or stepdown ratio is near but not equal to 1, as well as some alternatives to simple bucks and boosts.
Fig. 2 illustrates a tappedinductor buck or boost, which is an attractive candidate for small stepup and stepdown ratios. The only difference between this converter and the simple buck and boost of Fig. 1 is the second winding of the choke placed in series with the lower MOSFET (M_{LOWER}). The circuit in Fig. 1 is contained in the Fig. 2 circuit and represents the case in which the turns ratio of L_{LOWER} to L_{UPPER} is zero.
For Fig. 2, there will be a different set of CSFs for each turns ratio, and the turns ratio can be varied to achieve different results. We will consider the case where the load/line at the right side of the circuit is 380 V and the line/load at the left side of the circuit is 400 V at a power level of 400 W. We also will consider the minimumvoltage tappedinductor converter^{[1]}, shown in Fig. 3, for the small ratioconversion problem.
The Fig. 3 circuit is of minimum voltage in the sense that none of the transistors has voltage stress higher than the load/line voltages. Refer to part one of this article series for information on how to calculate the CSF for each component. Table 1 summarizes optimized results for Figs. 1, 2 and 3.
For the Fig. 2 circuit, if we optimize component weights for minimum total semiconductor component stress factor (SCSF), we find that the optimal turns ratio is 17.9 and we achieve a 20 times reduction in total semiconductor stress but at a cost. With a 17.9 turns ratio, the total winding component stress factor (WCSF) has almost doubled and the capacitor component stress factor (CCSF) has increased by almost two orders of magnitude.
In many applications, this may be a good tradeoff since the input capacitor requirement may be driven by an electromagnetic interference filter requirement or an interface stability issue, such as Middlebrooke's rule, and the output capacitor requirement may be driven by a load transient or ripple voltage requirement.
Table 2 also illustrates a compromise case where the turns ratio is selected to be 1to1. With a 1to1 turns ratio, a substantial improvement in total SCSF is realized with more modest degradations in total WCSF and total CCSF. The lower semiconductor component stresses are achieved by using a lowvoltage MOSFET for M_{UPPER}.
With a 17.9 turns ratio, M_{UPPER} has a voltage stress of just slightly greater than 40 V. The voltage stress on M_{UPPER} can be large during a startup transition in the buck implementation and during a shutdown transition in the boost implementation, without some mechanism to protect M_{UPPER} while the load/line voltage to line/load voltage differential is high.
Figs. 1 and 2 Turns ratio = 0  Fig. 2 Turns ratio = 17.9  Fig. 2 Turns ratio = 1  Fig. 3 Turns ratio = 11.1  

M_{UPPER} SCSF  1.29  0.04  0.4  0.036 
M_{LOWER} SCSF  0.3  0.038  0.12  0.019 
M_{RESET} SCSF  0  0  0  0.021 
Total SCSF  1.59  0.078  0.52  0.076 
L_{UPPER} WCSF  0  0.01  0.01  0.007 
L_{LOWER} WCSF  0.01  0.009  0.002  0.005 
Total WCSF  0.01  0.019  0.012  0.012 
C_{IN/OUT} CCSF  0.053  1.89  0.16  3.01 
C_{OUT/IN} CCSF  0  1.7  0.07  2.76 
C_{MIDDLE} CCSF  0  0  0  0.15 
Total CCSF  0.053  3.59  0.23  5.92 
Figs. 1 and 5 Turns ratio=0  Fig. 4 Turns ratio=5  Fig. 5 Turns ratio=9.14  Fig. 5 Turns ratio=3  Fig. 6 Turns ratio=5  

M_{UPPER} SCSF  40  1.61  13.4  13.7  6.4 
M_{LOWER} SCSF  120  2.96  12.6  20.6  11.8 
M_{RESET} SCSF  0  1.64  0  0  6.5 
Total SCSF  160  24.8  26.1  34.3  24.8 
L_{UPPER} WCSF  0  0.4  2.9  1.7  1.6 
L_{LOWER} WCSF  3.24  0.56  3  3.4  2.24 
Total WCSF  3.24  3.84  5.9  5.1  3.84 
C_{IN/OUT} CCSF  9  0.39  1.7  2.9  2.3 
C_{OUT/IN} CCSF  0  0.48  1.5  0.9  2.9 
C_{MIDDLE} CCSF  0  0.48  0  0  2.9 
Total CCSF  9  1.35  3.3  3.8  8.1 
One way to solve this problem is by keeping M_{UPPER} in its conducting state during the high differential voltage transition. All of the tappedinductor power converters in this article achieve efficiency improvements by using MOSFETs with lower voltage ratings than the peak dc voltages present in the circuit. One must consider the potential for the application of voltages higher than the steadystate voltages to lowvoltage MOSFETs during voltage transients, and implement necessary avoidance or protection mechanisms. Often, a single zener diode can eliminate the problem.
For a topology that has superior total SCSF and superior total WCSF, a high CCSF can be dealt with by employing an interleaved multiphase configuration. Paralleling multiphase subconverters has no effect on total SCSF or total WCSF, but multiphasing reduces total CCSF by a factor equal to or greater than the square of the number of parallel subconverters (Fig. 4).
In the Fig. 3 circuit, M_{RESET} operates in synchronization with M_{UPPER}. C_{MIDDLE} is charged during the time that M_{LOWER} conducts and is discharged when M_{UPPER} and M_{RESET} are on. Results for the Fig. 3 circuit indicate that it provides SCSF improvements that are slightly better than those achieved by the Fig. 2 circuit, but with much lower total WCSF and an even greater increase in total CCSF. There are practical zerovoltage switching (ZVS) variations for each of the figures illustrated, but the Fig. 3 circuit requires no additional active switches to accomplish ZVS. Another topology that might be a candidate for small step ratios is the isolated flyback converter with the secondary circuit connected to line and load but not to ground.
Another problem where candidate topologies exist that compete well with simple bucks and boosts is the problem of large step ratios. We consider the problem of stepping from 100 V to 1000 V and from 1000 V to 100 V in a 100W converter. We will not consider the effects of wide linevoltage variations at this time. The candidate topologies that we will consider are the buck and boost of Fig. 1, the tappedinductor buck and boost for large step changes (Fig. 5), the minimumvoltage tappedinductor buck and boost for large step changes (Fig. 6) and a multiphase implementation of the Fig. 6 circuit in which two parallel subconverters share the same set of three capacitors, illustrated in Fig. 4.
Table 2 illustrates the results achieved. The simple buck and boost converters of Fig. 1 have high SCSFs because the switches have both high voltage stress and high current stress. In the Fig. 5 circuit optimized for minimum total SCSF, M_{UPPER} has high voltage stress (slightly less than 2 kV) but low current stress, and M_{LOWER} has high current stress but low voltage stress (slightly less than 200 V). The circuit in Fig. 5 achieves a 6to1 reduction in total SCSF compared to that in Fig. 1. The Fig. 5 circuit also achieves a reduction in total CCSF, but total WCSF increases by almost a factor of 2.
The Fig. 6 circuit achieves slightly lower total SCSF than the Fig. 5 circuit and significantly lower WCSF, only about 20% higher than the simple buck and boost, but the total CCSF is only slightly lower than the Fig. 1 circuit and significantly higher than the tappedinductor circuit of Fig. 5. In the Fig. 6 circuit, the voltage stresses of M_{UPPER}, M_{LOWER} and M_{RESET} are 1000 V, 167 V and 833 V, respectively. We address the issue of high CCSF by implementing a twophase converter based on the Fig. 6 circuit in which the capacitors are shared between the two subconverters.
We use the rules presented in part one of this article series to calculate the total SCSF and total WCSF for the dual subconverter combination. Since we only have one set of capacitors, we must calculate CCSFs for each capacitor again, considering that the capacitor currents are a combination of currents from the two subconverters. Fortunately, the capacitor currents from the two subconverters cancel each other to a large extent due to the fact that the subconverters are operated 180° out of phase. For the MOSFET M_{UPPER1} the peak voltage stress is 1000 V, the onstate current is 0.0835 A and the duty cycle is 0.599. The rootmeansquare (RMS) current in M_{UPPER1} is:
By optimizing for minimum total SCSF, we find that the optimal weight for M_{UPPER1} is 0.992 and the sum of the semiconductor weights is 3.822. The SCSF for M_{UPPER1} is:
For M_{LOWER1} the SCSF is 2.96 and for M_{RESET1} the SCSF is 1.64, so that the total subconverter SCSF is 6.2. Since the second subconverter is identical to the first except for operating phase, its total subconverter SCSF is also 6.2. For the total SCSF for a combination of subconverters in part one of this article series, we defined:
where W_{I} is the semiconductor subconverter weight for subconverter I, is the sum of semiconductor weights and Total SCSF_{I} is the total SCSF for subconverter I. We want the two subconverters in a multiphase arrangement to be equal in every respect except phasing, so we will assign a semiconductor subconverter weight of 1 to each subconverter.
In this case:
For the combination of subconverters the total SCSF is:
which is the same result we had for Fig. 6. We would expect there to be no advantage or disadvantage to breaking the converter into two parallel subconverters — each operating at half power — and the calculated total SCSF confirms that fact.
For L_{LOWER2} the applied voltage is:
The RMS current in L_{LOWER2} is given by:
The weight assigned to L_{LOWER2} is 1.4 and the sum of the winding weights is 2.4. The CSF for L_{LOWER2} is:
For L_{UPPER2} the WCSF is 0.40 and the total WCSF for the subconverter is 0.96. We assign a winding subconverter weight of 1 to each subconverter so that the sum of the winding subconverter weights is 2. For the combined system:
which is identical to the total WCSF obtained for the singlephase circuit, as expected.
Finding the total CCSF for the Fig. 4 circuit presents a different problem, because the three capacitors shown in Fig. 4 are shared by two subconverters. We calculate each CCSF considering that the capacitor currents are formed by algebraic sums of currents from the two subconverters. We assume that subconverter 1 is beginning its operating cycle and subconverter 2 is halfway through its operating cycle.
The average line/load current is P/V_{LINE/LOAD}, or 0.1 A. For C_{IN/OUT} the capacitor current is the difference between the average line/load current and the sum of currents in M_{UPPER1} and M_{UPPER2}. At the beginning of an operating cycle for a duty cycle of (0.599  0.500) = 0.099, both M_{UPPER1} and M_{UPPER2} conduct so that the C_{IN/OUT} net current is 0.0835 A 1 0.0835 A 2 0.1 A = 0.067 A. In the subsequent phase of the operating cycle, M_{UPPER2} turns off and the net current is 0.0835 A 2 0.1 A =  0.0165 A. The duty cycle for the second phase is 0.401.
During the next phase of the operating cycle, with duty cycle equal to 0.099, M_{UPPER2} is on again and the net C_{IN/OUT} current is 0.067 A. During the last phase, M_{UPPER1} is off, the duty cycle is 0.401 and the current is 0.0165 A. The RMS current in C_{IN/OUT} is 0.033 A. To achieve optimal (minimal) total CCSF, a weight of 0.964 is assigned to C_{IN/OUT}. The sum of capacitor component weights is 3.364. We can now calculate a CCSF for C_{IN/OUT}:
For C_{OUT/IN} and C_{MIDDLE} the CCSF is 0.48, and the total CCSF for Fig. 4 is 1.346. Among the many benefits of parallel multiphase converters is muchreduced capacitor component stress, which translates directly into higher efficiency. Compared to Fig. 6, Fig. 4 has improved total CCSF by a factor of 6. In general, multiphasing improves total CCSF by a factor equal to or greater than the square of the number of subconverters, if the topology enables capacitor sharing. Comparing Fig. 4 with Fig. 1, we achieve muchimproved total SCSF and total CCSF, for a 20% increase in total WCSF, but with a much larger component count.
With sets of operating equations for candidate circuit topologies and a spreadsheet or other mathematical computation program, one can readily generate a set of numbers for numerical topological comparison using the CSF method. An Excel spreadsheet illustrating the calculations in this article is available at www.TechnicalWitts.com. Next month, in the third and final part of this article series, we will compare isolated topologies and consider the effects of wide linevoltage range on power converters.
References

Wittenbreder, E.H., “Tapped Inductor Power Conversion Networks,” U.S. Patent Application 60/757561. Available online at www.technicalwitts.com.