Power Electronics

Optimizing Accuracy of Hysteretic Control

In voltage-mode, hysteretic-controlled dc-dc converters, output capacitor-induced ripple and loop delay are the key sources of error in output voltage regulation.

For the PDF version of this feature, click here.

Hysteretic control, also known as bang-bang control or ripple regulator control, maintains the converter output voltage within the hysteresis band centered about the reference voltage. The hysteretic-controlled regulator is popular because of its inexpensive, simple and easy-to-use architecture. The greatest benefits of hysteretic control are that it offers fast load transient response and eliminates the need for feedback-loop compensation. The other well-known characteristic is the varying operating frequency.[1-4]

However, the regulation inaccuracy issue of the hysteretic-controlled converter is almost unknown to engineers. Until now, research on hysteretic regulators has mainly focused on transient analysis and transient modeling.[1-3] The first analysis of accuracy was performed on a current-mode hysteretic regulator specifically designed to power microprocessors.[5] However, the regulation accuracy of the more widely used voltage-mode hysteretic-controlled regulators is still unknown.

By analyzing operation of the voltage-mode hysteretic-controlled regulator, the root cause of its inaccuracy can be identified. This analysis also reveals how operating conditions (input voltage [VIN]; output voltage [VOUT]; and loop delay [tD]), component sizes (inductor L, output capacitor C) and parasitic parameters (ESR, ESL, RDS(ON), DCR, etc.) affect the accuracy of dc regulation. Most importantly, this analysis influences the design process for hysteretic-controlled dc-dc converters and enables practical design tradeoffs to be made.

Sources of Inaccuracy

Fig. 1 shows a simplified hysteretic-controlled voltage regulator and its ideal operating waveforms with only ESR-caused output voltage ripple considered. If output voltage VO(t) is at or below the level of the reference VREF minus the hysteresis VHYS, output of the hysteretic comparator is high and then Q2 is turned off and Q1 is turned on. This is the power stage on-state and it causes the output voltage to increase.

When the output voltage VO(t) reaches or exceeds the reference VREF plus the hysteresis VHYS, the output of the hysteretic comparator turns low and then Q1 is turned off and Q2 is turned on. This is the power stage off-state, and it causes the output voltage to decrease. This hysteretic method of control keeps output voltage within the hysteresis band around the reference voltage, which leads the dc value of output voltage to be the reference voltage, namely VO=VREF, without any dc offset.

This conclusion is based on the assumptions that there is only ESR-caused output voltage ripple and that all components used are ideal. However, in practical applications, these assumptions are wrong. Output voltage ripple also includes output capacitor CO-caused ripple and ESL-caused ripple. And all components used are not ideal, so there will be delay in the whole control loop. Given these realities, can the dc regulation accuracy of a typical hysteretic-controlled regulator used in real applications be guaranteed?

Effects of ESL-Caused and CO-Caused Ripple

It is well known that output voltage ripple has three elements. The three elements of the output capacitor that contribute to output voltage ripple are ESR, ESL and capacitor CO. Assume that all three elements are in series and there are no other parasitic components to consider. Fig. 2 shows the voltage waveforms across each component of the output capacitor. These waveforms are described by the following equations. These equations define the ESR voltage components differently depending on whether the high-side MOSFET Q1 is turned on or the low-side MOSFET Q2 is turned on.

The voltage waveform across ESR with Q1 turned on is:

With Q2 turned on, that value becomes:

Similarly, the voltage waveform across the ESL when Q1 is on is:

which, when Q2 is on, becomes:

The last component of the ripple voltage waveform is the voltage waveform across an ideal capacitor with an initial value at the beginning of high-side Q1 on-time of:

which, at the beginning of low-side Q2 turn on, becomes:

From those components, the output voltage ripple waveform can be described as:

The ripple component from ESL causes the voltage steps; ESR causes the ramps; and capacitance causes the curvature in the ripple voltage during the switching transitions.[4]

First, let's consider the effect of ESL-caused ripple on the dc accuracy. Assume that ESL-caused voltage step is smaller than VHYS and Fig. 3 shows the output voltage waveform with only ESR- and ESL-caused ripple considered. From this figure, we can see that the output voltage's peak ripple above VREF is equal to VHYS, and the output voltage's valley ripple below VREF is equal to VHYS, too. Then the dc value of output voltage is still regulated at VREF without any offset. So ESL-caused ripple has no effect on the dc regulation accuracy as long as it is smaller than the hysteresis band.

Next, let's consider the output capacitor CO-caused ripple's effect on the dc accuracy. There are two cases that need to be considered. The first case is that CO is big and so CO-caused output ripple is small compared with ESR-caused ripple. The output voltage waveform in this case is shown in Fig. 4. Here we can see that output ripple is not a ramp anymore and it has second-order curvature caused by CO-caused ripple. But the output voltage's peak and valley value is still decided by ESR-caused ripple.

In this case, the output voltage's peak ripple above VREF is equal to VHYS, and the output voltage's valley ripple below VREF is equal to VHYS, too. So, the dc value of the output voltage is still regulated at VREF without any offset. That means CO-caused ripple has no effect on the dc regulation accuracy as long as it does not change the ESR-caused peak value of output ripple voltage.

In the second case, where CO is not very big, CO-caused output ripple cannot be ignored when compared with ESR-caused output ripple. The output voltage waveform in this case is shown in Fig. 5. From this figure, we can see the curvature of ripple is obvious and the output voltage's peak ripple does not happen at the end of on-time anymore. Now the output voltage's peak ripple happens at the same time during off-time, and it is decided by both CO-caused and ESR-caused ripple. In this case, the output voltage's peak ripple above VREF is higher than VHYS, and the output voltage's valley ripple below VREF is still equal to VHYS. Therefore, the dc value of output voltage is not regulated at VREF anymore. The offset between the dc value of output voltage and its target is equal to half of the output ripple voltage's overshoot over the upper hysteresis band VHYS, namely VOS=0.5(VPEAK_OFF - VHYS).

From this derivation, it can be seen that, for the hysteretic-controlled regulator, CO may influence the dc regulation accuracy depending on CO's value. In the following analysis, the range of CO's value for the second case and the output voltage dc offset in this case are provided.

From the ripple equations given for Fig. 2, the ripple of output voltage during off-time when only ESR- and CO-caused ripple are considered is:

where ΔI is the ripple current through the output capacitor CO and D is the duty cycle.

So, the peak value of VO_OFF happens at tOFF_MAX when:

From Eq. 2, we get:

Inserting Eq. 3 into Eq. 1, we can get the peak value of output voltage ripple during off-time:

Therefore, the case where the output ripple voltage's peak value occurs during the off-time happens when VPEAK_OFF is higher than the upper hysteresis band VHYS(VHYSເ0.5×ESR×ΔI). Then from Eqs. 3, 4 and 0 ≤t ≤ (1-D)TS, we can derive the boundary of CO when VPEAK_OFF is higher than VHYS:

The dc offset of output voltage under this condition is:

The Effect of Delay

In a hysteretic-controlled regulator, one important nonideal factor is the loop delay. Fig. 6 shows the output voltage waveform with only delay and ESR-caused ripple considered. From this figure, we can see that the output voltage's peak ripple above VREF is greater than VHYS, and the magnitude of the output voltage's valley ripple below VREF is also greater than VHYS. From Fig. 6, we can see that VOV, the overshoot over upper hysteresis band VHYs, and VUV, the undershoot over lower hysteresis band VHYS, are:

Then the dc value of output voltage, VOS_DELAY, is:

If we assume the rising delay time and the falling delay time are the same, namely tDR=tDF=tD, then:

From Eq. 9, we can see that the only time there is no dc offset is when VIN=2×VO, namely when the duty cycle is 50%. Under any other operating conditions, there will always be dc regulation offset caused by loop delay. And this offset is higher for lower inductance L, higher ESR, delay and the difference between VIN and VO.

Design Flow

From the previous analysis, we can see that hysteretic-controlled regulators may have inaccuracy issues in real applications. This inaccuracy is caused mainly by output voltage ripple elements other than ESR-caused ripple and by loop delay. In this section, a design example is presented to demonstrate a design flow for hysteretic voltage regulators that accounts for sources of dc error.

In this example, the hysteretic voltage regulator shown in Fig. 1a is used. And because the LM3475 hysteretic PFET buck controller is used, Q1 and Q2 in Fig. 1a should be changed to a PFET and a diode, respectively.[6] The design condition and target is: 5 V < VIN < 10 V, VO = VREF = 0.8 V, VHYS = 21 mV and load current IO = 1 A.

The operating frequency (fSW) and other performance characteristics of a hysteretic-controlled regulator depend on external conditions and components. The best approach is first to determine what operating frequency is desirable in the application. In this example, we assume the accepted operating frequency range is 200 kHz ≤ fSW ≤ 400 kHz.

From the operating frequency estimation equation given in reference 4 at the end of this article:

It is important that ESL meet the following condition: ESLD+VHYS×L/VIN. If it does not, the switching frequency becomes too high and uncontrollable. If CO is big enough and ESL is small enough, Eq. 10 can be simplified to be:

The peak-to-peak voltage ripple estimation is:

Assume in this example that the peak-to-peak voltage ripple estimation is smaller than VRIPPLE_SPEC=40 mV. Then we have:

Eqs. 10 and 11 show that the switching frequency and the output ripple strongly depend on L, ESR and ESL.

The minimum inductance can be calculated using the following equation:

where ΔI is the allowable inductor ripple current and VD is the forward voltage drop of the diode. The maximum allowable inductor ripple current should be calculated as a function of output current as shown here:

ΔIMAX=IOUT×0.3=0.3 A

Then, by Eq. 12 with fSW=300 kHz, the inductance L is chosen to be L=10 µH.

Once the inductance value and the desired operating frequency are selected, ESR must be selected based on Eq. 10 or 10a. By using Eq. 10a and tD≈100 ns for the required operating frequency range, ESR needs to be 70 mΩ ≤ ESR ≤ 170 mΩ. Here we choose ESR=100 mΩ. And this ESR value also needs to satisfy the ripple requirement given in Eq. 11.

Based on the previous analysis of CO-caused ripple, CO's affect on the dc regulation accuracy and operating frequency can be eliminated, if for duty cycle D < 0.5:

This equation dictates that CO≥23 µF for fSW=200 kHz and CO≥11 µF for fSW=400 kHz. Here we can choose CO=47 µF, CO=100 µF or CO=22 µF. Eq. 13 is a conservative estimation of the critical output capacitance because its derivation does not consider the turn-on and turn-off delay. So in real application, CO can be 22 µF without any affect on dc accuracy.

Once CO's choice satisfies Eq. 13, the dc regulation inaccuracy is mainly caused by the loop delay. In this case, the dc output voltage offset is:

This offset will be higher when L is lower, ESR is higher, delay is longer, and the difference between VIN and VO is greater. If this inaccuracy is not tolerable, the above design steps need to be repeated. Sometimes, it may take several iterations to satisfy all requirements.

As for the selection of other components, such as the input capacitor, diode and MOSFET, it is the same as that in the normal selection process. Bench test results for the component values selected previously are presented in Fig. 7. In Fig. 7, channel 1 is the switch node waveform and channel 3 is the output voltage. From Fig. 7, we can see circuit operation meets the design goal.


  1. Miftakhutdinov, R. “An Analytical Comparison of Alternative Control Techniques for Powering Next Generation Microprocessors,” TI Seminar, 2002.

  2. Yan, Liu, and Sen, P.C. “Large-Signal Modeling of Hysteretic Current-Programmed Converters,” IEEE Trans. on Power Electronics, Vol. 11, No. 3, 1996, pp. 423-430.

  3. Tso, C., and Wu, J. “A Ripple Control Buck Regulator with Fixed Output Frequency,” IEEE Power Electronics Letters, Vol. 1, No. 3, 2003, pp. 61-63.

  4. “Designing Fast Response Synchronous Buck Regulators Using the TPS5211,” User's Guide, Texas Instruments, June 2000.

  5. Song, C., and Nilles, J. “Accuracy Analysis of Hysteretic Current-Mode Voltage Regulator,” Proc. IEEE APEC, 2005, pp. 276-280.

  6. “LM3475 Datasheet,” National Semiconductor Corp., January 2005.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.