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Power supply designers are under constant pressure to wring improvements in thermal density and power capacity in new designs, yet market cost pressures do not favor an extended R&D cycle and the costs that resonant technologies may require to bring products to market. Even with the advent and wide adoption of firstgeneration superjunction MOSFETs, designers are sometimes surprised to find that adding transistors in parallel is no panacea or easy path to efficiency improvements.
This article examines the use of published transistor data for existing and emerging highvoltage MOSFET technologies, and discusses how to apply this data for a more accurate prediction of switching losses in two common hardswitching applications: offline power factor correction (PFC) and the forward converter. This is facilitated by breaking down the MOSFET loss components into the components due to discharging of the intrinsic output capacitance and those due to timevariable crossover losses. These losses will be examined in the context of PFC converters at several power levels. In addition, the article examines how closely an optimized interleaved twotransistor forward converter can approach the efficiency and power density of the popular phaseshift ZVS bridge converter through topology and component optimization.
MOSFET AreaSpecific Performance
While it's true semiconductor manufacturers have yet to deliver the ideal switch, it is also recognized that steady advances have been made in the lowvoltage area over the last 20 years. During this period, new and improved generations of lowvoltage MOSFETs have been released about every three years. However, until relatively recently, that hasn't been the case for highvoltage MOSFETs.
For conventional highvoltage MOSFETs, the voltage blocking capability in the drain drift region is developed through the combination of a thick region epitaxial region and light doping. This results in about 95% of the device resistance in the drain, which cannot be improved by the approaches used for lowvoltage transistors (cell shrink, Trench cells and smaller cell pitch), where only about 30% of the transistor resistance is in the drain drift region. The intrinsic resistance of a conventional epitaxial drift region for a given breakdown voltage is the “silicon limit line,” which, in the past, has been a barrier to improved performance in highvoltage MOSFETs.
In 1999, the first superjunction MOSFETs were introduced commercially by Siemens^{[1]} (Munich, Germany), followed later by ST Microelectronics^{[2]} (Geneva, Switzerland), employing a novel drain structure (Fig. 1).
There are two key principles employed in this transistor design. First, the main current path is more heavily doped (by a factor of 10) than for a conventional highvoltage MOSFET. This lowers the onstate resistance of the drain. But without the pcolumns under the cell structure, which is the charge compensation structure, we might just have a 100V transistor instead of a 600V device.
The current path of the pcolumn and ndoped structures are dimensioned so that when the transistor is turning off and developing blocking voltage, the resulting depletion region forms with migration of the charge carriers from the pdoped columns, resulting in a nearneutral space charge region and high blockingvoltage capability. The reduction in resistance has obvious conduction loss benefits; the attendant fivefold reduction in chip area for the first generation of this technology lowered capacitance and dynamic losses as well. This technology made it possible to “beat” the silicon limit line (Fig. 2) and, with a new 7.5µm pitch generation, to improve all aspects of losses still further.
The importance of areaspecific loss balance for highvoltage transistors becomes increasingly important as we seek higher power densities through better efficiency (lower losses) and higher switching frequencies (to reduce transformer, inductor and capacitor component size). The tradeoffs in loss balance are illustrated in Fig. 3, where the case of a transistor switching 400 V at 200 kHz with a load current of 1 A is considered. Conduction and dynamic losses are plotted for both the last standardgeneration DMOS and for firstgeneration superjunction MOSFET (CoolMOS). Higher load currents and lower switching frequency can shift the balance point for areaspecific losses in a given MOSFET technology, but in all cases, transistors with better areaspecific R_{ON} and lower capacitance, if used properly, can deliver the lowest losses.
MOSFET capacitance is nonlinear, so even standard DMOS transistors have a strong voltage dependency on the thickness of the depletion region and the resulting output capacitance. Superjunction MOSFETs show a stronger nonlinearity of capacitance, due to the large area for the output capacitance at low voltage formed by the pcolumns. This nonlinearity further increases with the latestgeneration devices, as shown for C5 in Fig. 4.
The critical factor here is that the energy increases as a function of the square of the voltage, so that the low capacitance above 50 V does result in lower overall turnon losses from discharging C_{OSS} each switching cycle, as can be seen for calculations of similar R_{ON} devices in Fig. 5. Let's take a look at how that affects performance and transistor selection in two applications: an offline PFC boost converter and an interleaved forward converter operating from a PFC regulated bus.
Estimating Losses and Optimal Transistor Selection
Four factors contribute to power MOSFETrelated losses in a switching power supply:
Conduction losses:
where I_{Drain} is the MOSFET drain current, and D_{Max} is the duty cycle for conduction.
Switching crossover losses:
where V_{DS} is the drain switching voltage, and f_{s} is the switching period frequency.
Turnon switching loss discharging the MOSFET output capacitance:
where C_{O(ER)} is the energyrelated equivalent value for output capacitance integrated over the range from 0 V to 480 V, and the gatedriver power loss is:
Pd_{GATE}=Q_{G}×V_{GATE}×f_{S}
where Q_{G} is the MOSFET gate charge at the operating gate voltage (V_{GS}).
The total MOSFET loss is the sum of these components:
The crossover and C_{OSS} switching losses have often been lumped together as something of an oversimplification, as an accurate estimate of the output capacitance losses can't be derived using the common C_{OSS} spec. Instead, an integrated value, which is energy related, must be derived, and this value is available in CoolMOS datasheets. Also, the strongly nonlinear output capacitance of superjunction transistors lowers turnoff losses from the expected value, often by as much as 40%.
Let's examine how to estimate these losses and make an optimal transistor selection for the PFC boost converter switchedmode power supply (SMPS) front end and in the interleaved twotransistor forward converter.
PFC Boost Transistor Losses
The widerangeinput boost converter poses some special challenges for calculating the switch operating conditions, due to the range of line input voltage that may be encountered and the halfsinewave rectified waveform. An accurate calculation method must take into account the operating current, as it varies due to the rectified input voltage and the ripple current in the boost inductor^{[3]}.
Let's consider a 600W power supply with worstcase conditions requiring 750 W from the PFC during startup or brownout recovery, for a bulk bus of 400 V. A simple closedform equation, considering the required power out (650 W), the input rms voltage (75 V rms) and the expected brownout efficiency η (88%) will provide the peak input current:
But, calculating the conduction loss accurately requires evaluating the input and inductor ripple current on a pulsebypulse basis, determining those operating points over a complete ac cycle.
First, functions specifying the ac operating period and input voltage, with an indexed variable for time (t_{MAIN}), are defined:
Using the calculated value for rms input current, a waveform for the PFC line input current is calculated:
Using the same time range variable, the duty cycle over the waveform can be calculated for the MOSFET switch d_{SW} and the boost diode d_{D}.
Next, the ripple current (I) as a function of input voltage, PFC inductor, switching frequency and duty cycle is calculated for the on and off states.
The min and max switch current are calculated, as shown in Fig. 6:
And the instantaneous conduction losses as a function of these current and the expected R_{DS(ON)} for SPW35N60C3 at 100°C can be calculated from:
Lastly, integration of momentary values gives the average conduction loss for:
P_{S_COND_AVG}=12.19 W (Eq. 10)
Between the calculated peak current, the calculated losses and the proposed heatsink, a basic device selection is possible for a given inductor ripple current level independent of frequency by considering the total power losses and the thermal impedance to ambient. But, once we consider switching frequency, the device capacitances with their affect on the crossover and C_{OSS} losses, as well as the gate charge losses, must be considered in the final selection.
Some possible candidates with key characteristics for the boost switching FET are shown in the table. These are all 32A to 35A class MOSFETs, including a highperformance conventional 600V MOSFET (IRFPS38N60L), a C3 generation CoolMOS superjunction MOSFET (SPW35N60C3), and a new 7.5µm generation IPP60R099CS.
Let's consider C_{OSS} first. It's fixed by the MOSFET, regardless of what is done with the driver design. A plausible range for f_{S} would be from 67 kHz to as much as 250 kHz, depending on efficiency and power density goals. To simplify the C_{OSS} loss calculation, we'll use the average value of V_{DS} at turnon, using the inputvoltage range for highline conditions 265 Vac. Using the previous equation for Pd_{COSS}, for a switching frequency of 67 kHz, the C_{OSS} loss estimate for the conventional 600V MOSFET is approximately 1.5 W, with gate charge losses of about 200 mW. The conduction losses also are higher, about 18 W, and crossover losses will be dependent on available gatedrive current and the resulting switching fall time, which is under the control of the SMPS designer.
As shown in the CPES study^{[4]}, the MOSFET conduction and switching losses are deciding factors in overall efficiency, even when a low switching loss boost rectifier such as a silicon carbide Schottky is used. With 2.5 A of gate drive available, bestcase switching time will be approximately 90 ns, with switching crossover losses of about 9 W.
Note that under nominal (120 Vac) or highline conditions, these switching loss components may start to dominate the loss picture, even at this low switching frequency. What happens if the design requirements dictate reducing the PFC inductor value to shrink the core volume through raising the switching frequency? Going from 67 kHz to 250 kHz will nearly quadruple the “fixed” switching loss overhead in this example, raising it to about 6 W for Pd^{COSS}, and 0.6 W for gatedrive power. This would lower efficiency by 1.1% under otherwise equivalent conditions before including the crossover losses.
However, the main problem is crossover losses. With a 2.5A gate driver, the predicted losses are over 30 W, which would cost 5% in efficiency. With a 10A gate driver, this could be reduced to slightly over 9 W, only a 1.5% efficiency penalty. Clearly, this tends to block the use of higher switching frequencies with conventional highvoltage MOSFETs.
How do the superjunction MOSFETs fare in comparison and on what basis would a transistor selection be made? Conduction losses are essentially identical, so the focus will be on the switching loss characteristics. Let's consider a 130kHz clock for both to compare the differences. For the SPW35N60C3, the fixed switching losses from Pd_{Coss} and gate charge total a little over 2 W. For the IPP60R099CS, it's about 1.6 W. Crossover switching losses is where it may become more a matter of economics. For an integrated PFC + driver IC, the IPP60R099 can be driven to 14 ns t_{ON} and t_{OFF}, with crossover switching losses under 75 Vac conditions estimated at 5.6 W. But the gate charge of the SPW35N60C3 is almost three times higher and with the same driver, and 10Ω R_{G} will only manage 45ns transitions and will exhibit crossover losses over 14 W.
With a 10A gate driver as suggested for the conventional 600V MOSFET, the crossover losses can be reduced to the 6W range, but at the additional expense of the higher gatedrive current. The CSgeneration superjunction MOSFET offers benefits with regard to system cost as well as system performance compared with existing superjunction transistors.
Note that these estimates for switching loss at the higher current range of PFC operation can be strongly influenced in practice by layout issues, especially gatelead inductance, source connection inductance and the size of the highfrequency power switch current loop. For the MOSFETs with larger input gate charge, keeping the parasitic inductance of the gate path low becomes highly important to good performance. For all devices, as switching currents approach and exceed 10 A, parasitic inductance can have an adverse affect on switching losses by extension of the gate plateau turnoff region, just as is the case for lowvoltage devices in fast switching applications^{[5]}.
Isolated PWM Stage ZVS and ITTF
For the highpower isolated output stage, the analysis is much simpler, as the PFCregulated 400V bus provides stable operating conditions for the converter. But which of several popular topologies should be used, and how can the transistor selection be optimized for these topologies?
The resonantswitching ZVS phaseshift bridge converter has become very popular since its invention over 20 years ago and is a fairly mainstream solution for SMPS supplies above 600 W. It requires some care in design to assure resonantswitching transitions with low turnon losses from at least half load up to full load. The selection of MOSFETs is critical because of the low output capacitance required to sustain resonant transitions at light load and the reliability issues with body diode commutation at light and no load, which mandate low Q_{RR} body diode characteristics^{[6,7]}. When combined with a current doubler output rectifier stage, the dual inductor approach minimizes current ripple, which the output capacitors must filter, thus improving inductor cooling through more surface area per core volume and minimizing the size of the output filter capacitor.
The interleaved forward converter, especially the interleaved twotransistor forward converter, offers an interesting alternative, which is shown in concept in Fig. 7. It features a simpler design process in comparison, having no need to balance MOSFET output capacitance, a resonant inductance (either explicit or implicit in the transformer primary characteristics) against PWM usable duty cycle and operating frequency. Traditionally, turnon losses in hard switching are higher, due to C_{OSS} discharge as well as MOSFET crossover losses, and commutation of secondaryside rectifier diodes (the freewheeling diode) and snubber networks. However, improved design techniques^{[8,9]}, including the optimization of secondaryside configuration and snubber network configurations, may make it a viable competitor.
To investigate if the new generation of superjunction transistors should offer further possibility for performance improvements, complete offline SMPS power supplies with identical PFC stages were designed and built in similar configurations operating at 130 kHz, excepting the isolated PWM output topology. For one, a ZVS phaseshift bridge with current doubler was used. For the other, a dual interleaved forward was implemented, with a dual output inductor secondary (Fig. 8).
The same IPP60R099CS transistors were used for the MOSFET switches in each converter. Component costs of the two designs only differed slightly. Results with both prototypes were good, showing peak efficiency of 92% to 93% (Fig. 9). Interestingly, the efficiency for the ITTF peaks at about 550 W, and at this point, it is ahead of the ZVS bridge, increasing to about 6% better at the 300W output level. This has interesting implications for N+1 redundant power supplies, where the normal operating power of the converter is typically 30% to 40% of output capability. In this situation, it seems the ITTF has the potential to deliver lower electrical costs and lower cooling costs.
Is this design fully optimized? Perhaps there's room for improvement with the forward converter transistors. The operating current at full load for the switches is:
Estimated crossover losses considering the 10Ω R_{G} and 2.5A gate driver are:
Conduction losses are calculated as:
While C_{OSS}related losses are:
Due to the ultralow gate charge, Pd_{GATE}=Q_{G}×V_{GATE}× F_{S}=0.1 W, which is of negligible concern. But clearly, even though this chip is small enough to fit in a TO220 package, it is oversized because conduction and switching losses are nowhere near in balance. Using the same calculations for the upcoming IPP60R199CP transistor, the same crossover loss occurs, but C_{OSS}related loss is cut in half to approximately 0.75 W, conduction loss only rises to 0.5 W, and total losses drop from 3.9 W to 3.3 W. In addition, costs are reduced with the much smaller chip in the forward transistor. The net gain is about 2.4 W of reduced power dissipation, notching the overall efficiency up about 0.24%.
Clearly, taking some care with evaluating the transistor characteristics and impact in the application will pay dividends for both performance and power system cost.
References

Deboy, G., März, M., Stengl, J., Strack, H., Tihanyi, J. and Wever, H. A New Generation of High Voltage MOSFETs Breaks the Limit of Silicon. Proc. IEDM 98, San Francisco, Calif., December 1998, pp. 26.2.126.2.3.

Saggio, M., Fagone, D. and Musumeci, S. MDmesh: Innovative Technology for High Voltage Power MOSFETs. Proc. ISPSD 200, Toulouse May 2000, pp. 6568.

Hancock, J.M. “Simplifying Power Factor Correction in SMPS,” Power Electronics Technology, October 2004, pp. 2635.

Lu, B., Dong, W., Zhao, Q. and Lee, F. Performance Evaluation of CoolMOS and SiC Diode for SinglePhase Power Factor Correction Applications. APEC 2003 Conference proceedings.

Elbanhawy, A. “Buck Converter Losses Under the Microscope,” Power Electronics Technology, February 2005, pp. 2432.

Saro, L., Dierberger, K. and Redl, R. HighVoltage MOSFET Behavior in SoftSwitching Converters: Analysis and Reliability Improvements. Proc. INTELEC 1998, San Francisco, Calif., October 1998, pp. 3040,.

Fiel, A. and Wu, Thomas. MOSFET Failure Modes in the ZeroVoltageSwitched FullBridge Switching Mode Power Supply Applications. Proc. APEC 2001.

Zhang, M., Jovanovic, M. and Lee, F. “Analysis and Evalution of Interleaving Techniques in Forward Converters.” IEEE Transactions on Power Electronics, Vol. 13, No. 4, July 1998.

Hriscu, L. and Casaru, G. Low Loss Snubbing in DCDC Converters. Proc. Electronica Power Electronics Conference April 2004, San Francisco.
MOSFET Part Number  R_{DS(ON)}  C_{O(ER)}  Q_{G} 

IRFPS38N60L  150 mΩ  260 pF  320 nC 
SPW35N60C3  100 mΩ  180 pF  150 nC 
IPP60N099CS  99 mΩ  130 pF  60 nC 