Power Electronics

Superjunction FETs Boost Efficiency in PWMs

Improved MOSFET technology enables a hard-switching PWM, the interleaved two-transistor forward converter, to approach the efficiency and power density of the popular phase-shift ZVS bridge converter in high-voltage applications.

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Power supply designers are under constant pressure to wring improvements in thermal density and power capacity in new designs, yet market cost pressures do not favor an extended R&D cycle and the costs that resonant technologies may require to bring products to market. Even with the advent and wide adoption of first-generation superjunction MOSFETs, designers are sometimes surprised to find that adding transistors in parallel is no panacea or easy path to efficiency improvements.

This article examines the use of published transistor data for existing and emerging high-voltage MOSFET technologies, and discusses how to apply this data for a more accurate prediction of switching losses in two common hard-switching applications: off-line power factor correction (PFC) and the forward converter. This is facilitated by breaking down the MOSFET loss components into the components due to discharging of the intrinsic output capacitance and those due to time-variable crossover losses. These losses will be examined in the context of PFC converters at several power levels. In addition, the article examines how closely an optimized interleaved two-transistor forward converter can approach the efficiency and power density of the popular phase-shift ZVS bridge converter through topology and component optimization.

MOSFET Area-Specific Performance

While it's true semiconductor manufacturers have yet to deliver the ideal switch, it is also recognized that steady advances have been made in the low-voltage area over the last 20 years. During this period, new and improved generations of low-voltage MOSFETs have been released about every three years. However, until relatively recently, that hasn't been the case for high-voltage MOSFETs.

For conventional high-voltage MOSFETs, the voltage blocking capability in the drain drift region is developed through the combination of a thick region epitaxial region and light doping. This results in about 95% of the device resistance in the drain, which cannot be improved by the approaches used for low-voltage transistors (cell shrink, Trench cells and smaller cell pitch), where only about 30% of the transistor resistance is in the drain drift region. The intrinsic resistance of a conventional epitaxial drift region for a given breakdown voltage is the “silicon limit line,” which, in the past, has been a barrier to improved performance in high-voltage MOSFETs.

In 1999, the first superjunction MOSFETs were introduced commercially by Siemens[1] (Munich, Germany), followed later by ST Microelectronics[2] (Geneva, Switzerland), employing a novel drain structure (Fig. 1).

There are two key principles employed in this transistor design. First, the main current path is more heavily doped (by a factor of 10) than for a conventional high-voltage MOSFET. This lowers the on-state resistance of the drain. But without the p-columns under the cell structure, which is the charge compensation structure, we might just have a 100-V transistor instead of a 600-V device.

The current path of the p-column and n-doped structures are dimensioned so that when the transistor is turning off and developing blocking voltage, the resulting depletion region forms with migration of the charge carriers from the p-doped columns, resulting in a near-neutral space charge region and high blocking-voltage capability. The reduction in resistance has obvious conduction loss benefits; the attendant five-fold reduction in chip area for the first generation of this technology lowered capacitance and dynamic losses as well. This technology made it possible to “beat” the silicon limit line (Fig. 2) and, with a new 7.5-µm pitch generation, to improve all aspects of losses still further.

The importance of area-specific loss balance for high-voltage transistors becomes increasingly important as we seek higher power densities through better efficiency (lower losses) and higher switching frequencies (to reduce transformer, inductor and capacitor component size). The tradeoffs in loss balance are illustrated in Fig. 3, where the case of a transistor switching 400 V at 200 kHz with a load current of 1 A is considered. Conduction and dynamic losses are plotted for both the last standard-generation DMOS and for first-generation superjunction MOSFET (CoolMOS). Higher load currents and lower switching frequency can shift the balance point for area-specific losses in a given MOSFET technology, but in all cases, transistors with better area-specific RON and lower capacitance, if used properly, can deliver the lowest losses.

MOSFET capacitance is nonlinear, so even standard DMOS transistors have a strong voltage dependency on the thickness of the depletion region and the resulting output capacitance. Superjunction MOSFETs show a stronger nonlinearity of capacitance, due to the large area for the output capacitance at low voltage formed by the p-columns. This nonlinearity further increases with the latest-generation devices, as shown for C5 in Fig. 4.

The critical factor here is that the energy increases as a function of the square of the voltage, so that the low capacitance above 50 V does result in lower overall turn-on losses from discharging COSS each switching cycle, as can be seen for calculations of similar RON devices in Fig. 5. Let's take a look at how that affects performance and transistor selection in two applications: an off-line PFC boost converter and an interleaved forward converter operating from a PFC regulated bus.

Estimating Losses and Optimal Transistor Selection

Four factors contribute to power MOSFET-related losses in a switching power supply:

Conduction losses:

where IDrain is the MOSFET drain current, and DMax is the duty cycle for conduction.

Switching crossover losses:

where VDS is the drain switching voltage, and fs is the switching period frequency.

Turn-on switching loss discharging the MOSFET output capacitance:

where CO(ER) is the energy-related equivalent value for output capacitance integrated over the range from 0 V to 480 V, and the gate-driver power loss is:


where QG is the MOSFET gate charge at the operating gate voltage (VGS).

The total MOSFET loss is the sum of these components:

The crossover and COSS switching losses have often been lumped together as something of an oversimplification, as an accurate estimate of the output capacitance losses can't be derived using the common COSS spec. Instead, an integrated value, which is energy related, must be derived, and this value is available in CoolMOS datasheets. Also, the strongly nonlinear output capacitance of superjunction transistors lowers turn-off losses from the expected value, often by as much as 40%.

Let's examine how to estimate these losses and make an optimal transistor selection for the PFC boost converter switched-mode power supply (SMPS) front end and in the interleaved two-transistor forward converter.

PFC Boost Transistor Losses

The wide-range-input boost converter poses some special challenges for calculating the switch operating conditions, due to the range of line input voltage that may be encountered and the half-sinewave rectified waveform. An accurate calculation method must take into account the operating current, as it varies due to the rectified input voltage and the ripple current in the boost inductor[3].

Let's consider a 600-W power supply with worst-case conditions requiring 750 W from the PFC during startup or brownout recovery, for a bulk bus of 400 V. A simple closed-form equation, considering the required power out (650 W), the input rms voltage (75 V rms) and the expected brownout efficiency η (88%) will provide the peak input current:

But, calculating the conduction loss accurately requires evaluating the input and inductor ripple current on a pulse-by-pulse basis, determining those operating points over a complete ac cycle.

First, functions specifying the ac operating period and input voltage, with an indexed variable for time (tMAIN), are defined:

Using the calculated value for rms input current, a waveform for the PFC line input current is calculated:

Using the same time range variable, the duty cycle over the waveform can be calculated for the MOSFET switch dSW and the boost diode dD.

Next, the ripple current (I) as a function of input voltage, PFC inductor, switching frequency and duty cycle is calculated for the on and off states.

The min and max switch current are calculated, as shown in Fig. 6:

And the instantaneous conduction losses as a function of these current and the expected RDS(ON) for SPW35N60C3 at 100°C can be calculated from:

Lastly, integration of momentary values gives the average conduction loss for:

PS_COND_AVG=12.19 W (Eq. 10)

Between the calculated peak current, the calculated losses and the proposed heatsink, a basic device selection is possible for a given inductor ripple current level independent of frequency by considering the total power losses and the thermal impedance to ambient. But, once we consider switching frequency, the device capacitances with their affect on the crossover and COSS losses, as well as the gate charge losses, must be considered in the final selection.

Some possible candidates with key characteristics for the boost switching FET are shown in the table. These are all 32-A to 35-A class MOSFETs, including a high-performance conventional 600-V MOSFET (IRFPS38N60L), a C3 generation CoolMOS superjunction MOSFET (SPW35N60C3), and a new 7.5-µm generation IPP60R099CS.

Let's consider COSS first. It's fixed by the MOSFET, regardless of what is done with the driver design. A plausible range for fS would be from 67 kHz to as much as 250 kHz, depending on efficiency and power density goals. To simplify the COSS loss calculation, we'll use the average value of VDS at turn-on, using the input-voltage range for high-line conditions 265 Vac. Using the previous equation for PdCOSS, for a switching frequency of 67 kHz, the COSS loss estimate for the conventional 600-V MOSFET is approximately 1.5 W, with gate charge losses of about 200 mW. The conduction losses also are higher, about 18 W, and crossover losses will be dependent on available gate-drive current and the resulting switching fall time, which is under the control of the SMPS designer.

As shown in the CPES study[4], the MOSFET conduction and switching losses are deciding factors in overall efficiency, even when a low switching loss boost rectifier such as a silicon carbide Schottky is used. With 2.5 A of gate drive available, best-case switching time will be approximately 90 ns, with switching crossover losses of about 9 W.

Note that under nominal (120 Vac) or high-line conditions, these switching loss components may start to dominate the loss picture, even at this low switching frequency. What happens if the design requirements dictate reducing the PFC inductor value to shrink the core volume through raising the switching frequency? Going from 67 kHz to 250 kHz will nearly quadruple the “fixed” switching loss overhead- in this example, raising it to about 6 W for PdCOSS, and 0.6 W for gate-drive power. This would lower efficiency by 1.1% under otherwise equivalent conditions before including the crossover losses.

However, the main problem is crossover losses. With a 2.5-A gate driver, the predicted losses are over 30 W, which would cost 5% in efficiency. With a 10-A gate driver, this could be reduced to slightly over 9 W, only a 1.5% efficiency penalty. Clearly, this tends to block the use of higher switching frequencies with conventional high-voltage MOSFETs.

How do the superjunction MOSFETs fare in comparison and on what basis would a transistor selection be made? Conduction losses are essentially identical, so the focus will be on the switching loss characteristics. Let's consider a 130-kHz clock for both to compare the differences. For the SPW35N60C3, the fixed switching losses from PdCoss and gate charge total a little over 2 W. For the IPP60R099CS, it's about 1.6 W. Crossover switching losses is where it may become more a matter of economics. For an integrated PFC + driver IC, the IPP60R099 can be driven to 14 ns tON and tOFF, with crossover switching losses under 75 Vac conditions estimated at 5.6 W. But the gate charge of the SPW35N60C3 is almost three times higher and with the same driver, and 10-Ω RG will only manage 45-ns transitions and will exhibit crossover losses over 14 W.

With a 10-A gate driver as suggested for the conventional 600-V MOSFET, the crossover losses can be reduced to the 6-W range, but at the additional expense of the higher gate-drive current. The CS-generation superjunction MOSFET offers benefits with regard to system cost as well as system performance compared with existing superjunction transistors.

Note that these estimates for switching loss at the higher current range of PFC operation can be strongly influenced in practice by layout issues, especially gate-lead inductance, source connection inductance and the size of the high-frequency power switch current loop. For the MOSFETs with larger input gate charge, keeping the parasitic inductance of the gate path low becomes highly important to good performance. For all devices, as switching currents approach and exceed 10 A, parasitic inductance can have an adverse affect on switching losses by extension of the gate plateau turn-off region, just as is the case for low-voltage devices in fast switching applications[5].

Isolated PWM Stage ZVS and ITTF

For the high-power isolated output stage, the analysis is much simpler, as the PFC-regulated 400-V bus provides stable operating conditions for the converter. But which of several popular topologies should be used, and how can the transistor selection be optimized for these topologies?

The resonant-switching ZVS phase-shift bridge converter has become very popular since its invention over 20 years ago and is a fairly mainstream solution for SMPS supplies above 600 W. It requires some care in design to assure resonant-switching transitions with low turn-on losses from at least half load up to full load. The selection of MOSFETs is critical because of the low output capacitance required to sustain resonant transitions at light load and the reliability issues with body diode commutation at light and no load, which mandate low QRR body diode characteristics[6,7]. When combined with a current doubler output rectifier stage, the dual inductor approach minimizes current ripple, which the output capacitors must filter, thus improving inductor cooling through more surface area per core volume and minimizing the size of the output filter capacitor.

The interleaved forward converter, especially the interleaved two-transistor forward converter, offers an interesting alternative, which is shown in concept in Fig. 7. It features a simpler design process in comparison, having no need to balance MOSFET output capacitance, a resonant inductance (either explicit or implicit in the transformer primary characteristics) against PWM usable duty cycle and operating frequency. Traditionally, turn-on losses in hard switching are higher, due to COSS discharge as well as MOSFET crossover losses, and commutation of secondary-side rectifier diodes (the freewheeling diode) and snubber networks. However, improved design techniques[8,9], including the optimization of secondary-side configuration and snubber network configurations, may make it a viable competitor.

To investigate if the new generation of superjunction transistors should offer further possibility for performance improvements, complete off-line SMPS power supplies with identical PFC stages were designed and built in similar configurations operating at 130 kHz, excepting the isolated PWM output topology. For one, a ZVS phase-shift bridge with current doubler was used. For the other, a dual interleaved forward was implemented, with a dual output inductor secondary (Fig. 8).

The same IPP60R099CS transistors were used for the MOSFET switches in each converter. Component costs of the two designs only differed slightly. Results with both prototypes were good, showing peak efficiency of 92% to 93% (Fig. 9). Interestingly, the efficiency for the ITTF peaks at about 550 W, and at this point, it is ahead of the ZVS bridge, increasing to about 6% better at the 300-W output level. This has interesting implications for N+1 redundant power supplies, where the normal operating power of the converter is typically 30% to 40% of output capability. In this situation, it seems the ITTF has the potential to deliver lower electrical costs and lower cooling costs.

Is this design fully optimized? Perhaps there's room for improvement with the forward converter transistors. The operating current at full load for the switches is:

Estimated crossover losses considering the 10-Ω RG and 2.5-A gate driver are:

Conduction losses are calculated as:

While COSS-related losses are:

Due to the ultra-low gate charge, PdGATE=QG×VGATE× FS=0.1 W, which is of negligible concern. But clearly, even though this chip is small enough to fit in a TO-220 package, it is oversized because conduction and switching losses are nowhere near in balance. Using the same calculations for the upcoming IPP60R199CP transistor, the same crossover loss occurs, but COSS-related loss is cut in half to approximately 0.75 W, conduction loss only rises to 0.5 W, and total losses drop from 3.9 W to 3.3 W. In addition, costs are reduced with the much smaller chip in the forward transistor. The net gain is about 2.4 W of reduced power dissipation, notching the overall efficiency up about 0.24%.

Clearly, taking some care with evaluating the transistor characteristics and impact in the application will pay dividends for both performance and power system cost.


  1. Deboy, G., März, M., Stengl, J., Strack, H., Tihanyi, J. and Wever, H. A New Generation of High Voltage MOSFETs Breaks the Limit of Silicon. Proc. IEDM 98, San Francisco, Calif., December 1998, pp. 26.2.1-26.2.3.

  2. Saggio, M., Fagone, D. and Musumeci, S. MDmesh: Innovative Technology for High Voltage Power MOSFETs. Proc. ISPSD 200, Toulouse May 2000, pp. 65-68.

  3. Hancock, J.M. “Simplifying Power Factor Correction in SMPS,” Power Electronics Technology, October 2004, pp. 26-35.

  4. Lu, B., Dong, W., Zhao, Q. and Lee, F. Performance Evaluation of CoolMOS and SiC Diode for Single-Phase Power Factor Correction Applications. APEC 2003 Conference proceedings.

  5. Elbanhawy, A. “Buck Converter Losses Under the Microscope,” Power Electronics Technology, February 2005, pp. 24-32.

  6. Saro, L., Dierberger, K. and Redl, R. High-Voltage MOSFET Behavior in Soft-Switching Converters: Analysis and Reliability Improvements. Proc. INTELEC 1998, San Francisco, Calif., October 1998, pp. 30-40,.

  7. Fiel, A. and Wu, Thomas. MOSFET Failure Modes in the Zero-Voltage-Switched Full-Bridge Switching Mode Power Supply Applications. Proc. APEC 2001.

  8. Zhang, M., Jovanovic, M. and Lee, F. “Analysis and Evalution of Interleaving Techniques in Forward Converters.” IEEE Transactions on Power Electronics, Vol. 13, No. 4, July 1998.

  9. Hriscu, L. and Casaru, G. Low Loss Snubbing in DC-DC Converters. Proc. Electronica Power Electronics Conference April 2004, San Francisco.

Table. Selected 35-A, 600-V MOSFETs.
IRFPS38N60L 150 mΩ 260 pF 320 nC
SPW35N60C3 100 mΩ 180 pF 150 nC
IPP60N099CS 99 mΩ 130 pF 60 nC

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