Power Electronics

# Sugar and SPICE: Determining Input Bulk Capacitor for Switchmode Power Supplies

This is the first of a series of regular columns with tips and tricks for using SPICE to aid in the design of switchmode power supplies.

When the University of California at Berkeley released the simulation program with integrated circuit emphasis (SPICE) in the mid-1970s, it targeted analog IC designers. Their goal was to help these designers better predict the behavior of their silicon. Thanks to the effort of private software editors, the original software has evolved into affordable and easy-to-use packages, offering everything you need in terms of models and analysis tools.

Power electronics gained a large benefit from SPICE in the sense that marrying amps and volts no longer ended-up in smoke or heavy noise. In addition, you could simulate unstable systems without destroying anything — even if the output totally diverged from its initial operating point. Today, power libraries don't blow — and that's certainly one of the best arguments in favor of a simulation package.

Our first example tackles bulk capacitor selection in the front-end stage of any power supply. Fig. 1 shows the ripple superimposed over the dc rail. With a few algebraic lines, you can quickly derive the diode conduction time as follows:

Where:
Tc=Diode conduction time
Vmin=Valley ripple
Vacin=AC line input
Fline=Mains frequency

In addition, the necessary value for the bulk capacitor to fulfill the ripple requirements imposed by design constraints:

Where:
Cbulk=Bulk capacitor value in μF
Vripple=Ripple voltage
Vpeak=Peak ripple voltage
Pout=Delivered output power

Suppose you would like to assess the ripple evolution, and thus the rms current circulating in Cbulk over the whole input voltage range of your power supply. Fig. 2, on page 42, offers an interesting solution: instead of wiring a standard resistor whose value should be permanently adjusted to emulate the SMPS consumption (e.g. 70W kept constant by the feedback loop), a B-element source can easily do the job. Using an in-line equation, the following line automatically adjusts the current drawn from the line to keep the product V × I equal to the power parameter:

IsSpice4 B1 out 0 I=70/V(out)
PSpice G1 out 0 value={70/V(out)}

With such a line, whatever the rail voltage out, the load permanently draws 70W and eases the total range sweep. Because of the possible division by zero, you need to place an IC statement after the capacitor value as exemplified in the figure. An UIC keyword will tell the simulator to start with this initial voltage during the bias point calculation and everything should properly converge.

If you want the simulator to automatically find the capacitor value offering a given ripple (e.g. 20Vpp), a simple objective function can do the job, providing your simulator features an optimizer. In IsSpice4, you would authorize the simulator to vary CBulk ± 85% from an arbitrary value (beginning with 500 μF), and you would include an objective function to help find the capacitor value that will bring it close to zero. It could look like:

setcursor 0 35m
setcursor 1 45m
ofunc=(pk_pk(vout)-20)^2
print ofunc

The first two lines instruct the simulator to isolate a 10 ms period between 35 ms to 45 ms. Then define a measurement that will minimize when you get your answer. This is the ofunc statement that delivers zero when the peak-to-peak ripple reaches 20V. During the simulation, the optimizer will sweep CBulk value to quickly bring ofunc close to zero. After a few seconds, you will read in the .OUT file as follows:

*Optimized Results*

cbulk: capacitance 263.123812U

Next month, we'll describe an electrical behavior via simple equations. This technique, also called Analog Behavioral Modelling (ABM) allows the designers to implement their own devices when first-order effects are only necessary.