Power Electronics

# Solving the Problem of Pulse-Skipping Oscillations

Getting rid of oscillations with the 1842/43 PWM controller turned out to be easier than thought.

The 1842/43 PWM controller is perhaps the most popular controller used in switchmode power supplies. It works fine, providing that duty cycle is less than 50%. While slope compensation circuits can solve many problems associated with oscillations beyond 50% duty cycle, they sometimes introduce a new problem — pulse-skipping oscillation. Let's look at some ways to overcome these kinds of oscillations.

Fig. 1 is a block diagram of UC1842/43 PWM copied from a Unitrode data sheet. A short description of pins in an 8-pin package sets the stage for understanding the part.

Pin 1 (Comp): Output of Error Amplifier (E/A), which normally attaches to a compensation circuit. The compensation circuit assures that poles and zeros of the Bode plot are arranged so the power supply, while having fast response to load variations, operates in a stable mode (for example, without any oscillations). The output of this amplifier is a dc voltage with small ripple at the switching frequency. Any other frequency present at this output causes power supply oscillations.

Pin 2 (Vfb): The negative input of the E/A, fed by a portion of the output voltage (feedback voltage). It is compared internally with a 2.5V reference voltage to regulate the output voltage.

Pin 3 (Current sense): This is the input to the current sense comparator, which accepts a voltage converted from the sense resistor that monitors the current of the main power supply switch. At the beginning of each switching cycle, the main switch starts to conduct current, ramping up until the voltage applied to Pin 3 overcomes the voltage fed from E/A, at which instant an internal flip-flop puts output (Pin 6) into the low state for the rest of the switching cycle.

Pin 4 (Rt/Ct): Oscillator input. Rt and Ct connected to this pin set the switching frequency operation. The voltage on this pin is a sawtooth.

Pin 5 (ground): Ground.

Pin 6 (Output): PWM output, which drives the main power supply switch.

Pin 7 (Vcc): Vcc.

Pin 8 (Vref): The internally regulated 5V reference.

Unitrode Application note U-96A (1) gives an example of a flyback switching regulator, using a 50% duty cycle UC3844 controller and therefore operating at duty cycles less than 50%. Application note U-97 (2) provides extensive explanation why oscillations occur at duty cycles greater than 50% and how to add slope compensation with an error signal to avoid this problem. Fig. 2, on page 30, (from the UC3842/3 data sheet) provides further information of how to add slope compensation.

### Working Model

Let's look at the problem and its cure for a step-up switchmode (boost) power supply. Fig. 3, on page 32, is a simplified drawing of a circuit built and tested.

The boost stage was followed by a constant 50% duty cycle push-pull converter, which — along with a 160Vdc output — provided an auxiliary winding feeding the controller and used as a feedback to the regulated 160V output. This power supply operates with a 33Vdc to 72Vdc input and delivers 0mA to 220mA at 160Vdc output. This is not restricted to the specific example covered here, but is common to all topologies in which slope compensation is used to overcome 50% duty cycle-related oscillations. It is common to all current mode controllers derived from the 3842/43-type family.

In Fig. 3, on page 32, MOSFET switch Q1, inductor L1, diode D1, and capacitor C4 form a classic boost stage switching converter, controlled by a PWM control mode controller, U1. Q2 and R1 add slope compensation in the exact configuration depicted in Fig. 2. To capture the plots, we used a 4-channel digital oscilloscope, the Tektronics TDS 420A.

Fig. 4, on page 32, shows a timing diagram at points of interest for the moment at which power supply operates without any problem. This is in complete agreement with what is expected. It is fed by 48V input and delivers 190mA.

Although we observed the above plots on a boost power supply, all other topologies derived from the boost, buck, and flyback have essentially similar waveforms.

Plot A depicts sawtooth at Pin 4 of U1.

Plot B shows Pin 1 (E/A output) of U1.

Plot C is a plot at Pin 3 (current sense) of U1.

Plot D reflects current of the main switch Q1, as measured on Rsense resistor.

The numbers 1 to 4 point to the ground (0V) level of the A to D plots. Number 1 is a ground of plot A, 2 of plot B, and so on.

Each switching cycle normally consists of two intervals: t-ON when Q1 conducts, and t-OFF when Q1 shuts off. At the start of each switching cycle, Q1 begins to conduct and current ramps up. The voltage on sense resistor, Rsense, causes current to flow via R2. This current is summed with current of slope compensation flowing via R1, and a resulting waveform of ramping voltage as depicted in plot C is applied to current sense Pin 3 of U1. Current sense comparator (Fig. 1, on page 28) constantly compares the amplitude of this voltage with voltage of the E/A (plot B in Fig. 4). At the instant of equality between the two, PWM Latch (Fig. 1) via Pin 6 of U1 shuts off Q1. As a result, current ceases to flow via Q1, causing a decline (dip) in plot C. The waveform nevertheless continues to ramp, but slower — boosted now only by slope compensation. Ramping at the t-OFF interval will hereafter be referred to as a “tail.”

At the end of the switching cycle, the sawtooth (plot A) is reset internally in U1 (which causes current sense input waveform in plot C to be reset also), and a new switching cycle begins.

Looking at Fig. 5, the only thing changed relative to Fig. 4 is an increase of the input voltage from 48V to 56V.

It's evident the power supply “went crazy.” Some switching cycles at plot D are entirely missing. At first, you may assume the compensation circuit is to blame. But look at plot B. This is an output of E/A, as measured by probe at channel 2 and it's perfectly okay! So, what's the problem? After many hours of desperation and perspiration, it became obvious the problem is with the t-OFF tail.

This tail is not supposed to have any influence on power supply operation, as it occurs at the off time of the duty cycle (t-OFF) and is reset at the beginning of each switching cycle. However, somehow it causes the controller in some situations to go out of control (Fig. 4, on page 32).

Let's look at Fig. 6, on page 33. By adding only a small signal Schottky diode, D2, from the output of U1 (Pin 6) to the Isense input (Pin 3), you can see that the remedy is surprisingly simple.

D2 clamps the tail during t-OFF time. That's all. Now look at Fig. 7, which depicts waveforms of an “enhanced” boost converter identical to the conditions shown in Fig. 5, on page 33. The magic worked! Now the tail is clamped during t-OFF, and all current pulses are present. After checking the circuit with and without D2, the findings were as follows:

• Without D2, the circuit was totally unpredictable, sometimes succeeding to work without oscillations at low input voltages if loaded by heavy loads, as shown in Fig. 4.
• With light loads, the oscillations were the worst: Skipping of about 20 cycles took place, in spite of E/A output providing perfect dc voltage all the time.
• With D2, clamping the tail under all conditions from no-load to full-load and the entire input voltage range, the circuit worked without any oscillations.

### References

1. U96-A Unitrode Application Note. A 25W Off-Line Flyback Switching Regulator, pp. 9-47; 9-51, Product & Applications Handbook, 1993-94.

2. U97 Unitrode Application Note. Modeling, Analysis and Compensation of the Current-Mode Converter, pp. 9-52; 9-57, Product & Applications Handbook, 1993-94.