Power Electronics

Retooling for the Power Challenges Ahead

For more than four decades, power electronics engineers have tapped advances in semiconductor devices and associated components to deliver power solutions to system developers. The mission to provide efficient and low-cost power solutions to electrical and electronic products continues unabated. However, the rate of progress seems modest when compared to digital electronics.

Systems exploiting digital technologies continue to make phenomenal progress each generation. The modern 90-nm CMOS-based 64-bit microprocessors are running at multi-GHz speed, and 32-bit DSPs are processing several gigabit instructions per second.

In the power arena, few suppliers have just begun to tap the benefits of 8-bit microcontrollers for supervisory functions, while others are extolling the virtues of digital control. Likewise, a small group in the UPS and motion-control applications field have exploited the merits of low-end, low-cost DSPs. In fact, the majority of high-end power ICs is in the 0.5 to 0.8 micron CMOS realm. Hence, by that standard, there's plenty more to be accomplished.

Nevertheless, it's heartening to know that power designers are leaving no stone unturned to narrow that gap. Although being on par with digital electronics isn't in the near future, recent progress indicates that power electronics designers are aggressively moving forward on all fronts, including magnetics. This was evident in the keynote talks given at the recent Power Electronics Technology Conference & Exhibition in Long Beach, Calif.

Keynoter Trey Burns, vice president of worldwide technologies at Artesyn Technologies, shed new light on the challenges facing power electronics engineers in the near future. International Rectifier's CEO Alex Lidow emphasized a new systems approach for tackling the challenges of emerging dc-dc converters that must power tomorrow's microprocessors, whose current requirements are steadily soaring with voltages dropping below 1 V and transient response of submicrosecond. To address these upcoming issues and achieve new levels of performance at lower cost in shorter design cycles, Lidow said that a holistic systems approach, from ac mains to the final point-of-load (POL) converter, is the way to go.

In his keynote address, Burns focused on readiness. He expressed his views on the tools and skills necessary to cope with the upcoming hurdles. Until now, Burns said, power electronics engineers have been able to respond to demanding requirements for higher power-conversion efficiencies, tighter voltage-regulation limits and faster load transients. However, he cautioned, as semiconductor technology continues to advance and the pressure on power electronics systems continues to skyrocket, power designers will need special tools, new talents and advanced technologies to deliver high-performance next-generation solutions.

As power dissipation densities soar, they're challenging our thermal management and packaging capabilities, noted Burns. For much higher levels of integration demanded by future designs, designers must exploit the advances in finer CMOS processes, as well as integration of passive components, he indicated. Burns suggested that while these advances will provide the traditional incremental growth, the major leap forward will come from leveraging digital technologies. However, exploiting digital technologies means acquiring new set of tools and skills, argued the keynoter. Some of these include circuit and system simulation, logic simulation, hardware description language (HDL) modeling, logic synthesis and communications protocol. Ultimately, that means retraining the power electronics engineer to think like a digital designer. To expedite this process, educational institutions, semiconductor and component suppliers, and power-supply manufacturers must soon start modifying their training programs. Thereby, we can ensure that both seasoned and new power electronics engineers are prepared to face the challenges ahead.

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