When designing or testing dc-dc converters with a wide input voltage range, we are invariably concerned with how the stresses in the power supply may change with respect to input/line variations. For example, when conducting stress testing or design validation, the designer needs to fix an input voltage for the test. However, it isn't obvious whether a given stress is going to be the highest at the maximum or at the minimum of the input voltage range. Or worse, somewhere in the middle of the input voltage range.

Further, designers used to working with one major topology may be quite surprised when they shift attention to another topology, because the rules can change suddenly. Knowing what input voltage represents the “worst” condition for a given stress has a lot to do with the topology at hand. For example, the peak switch current is higher at low input voltages for the boost and buck-boost; yet, it's the opposite for the buck, for which the worst case is at high input voltages. Further, during the design process similar puzzling concerns can arise. For example, should the inductor design be for the highest input or the lowest input voltage of the range? For a buck, it didn't seem to matter too much at what input voltage we design the inductor, but if the designer applies the same nonchalance to a boost or a buck-boost, there may be no power supply to put through any further testing.

As for voltage stresses, the worst condition will be at the maximum input voltage. Designers can easily figure out the required voltage ratings of the devices used, in any given topology. The same applies to load conditions. Maximum load is the worst condition, and that's what we need to design for and test. The important point is: Even while delivering constant maximum load, the internal currents of the power supply change their shape, peak values, rms, and average values in response to changes in input voltage.

A comprehensive table of design information covers all the three main topologies: buck, buck-boost, and boost (see the **table**, on page 20). We consider a power supply of any of these topologies operating at constant (maximum) load, with a fixed output voltage, whose input voltage varies. We predict the response of a given parameter to the resulting variation in duty cycle, and thereby determine the worst-case input test or design condition. Our purpose here is to determine how some of these vary and to thereby fix a worst-case design or test condition for each of them.

Equations are essentially cast in terms of the output voltage (V_{O}), max load (I_{O}), duty cycle (D), and inductor current ripple ratio (*r*). The input voltage (V_{IN}) is not included directly in the stress formulae, as D reflects the input voltage variation. The most important fact to keep in mind here when relating D to V_{IN} is that for all topologies, low D corresponds to high V_{IN} and a high D to low V_{IN} (since output voltage is considered fixed).

The design table includes the drops across the switch (V_{SW}) and diode (V_{D}) for all the topologies. Since these “drops” have become increasingly important with the present day situation of ever-decreasing input/output voltage rails, it doesn't make sense anymore to approximate them to zero, as is often done in related literature. Thus, the **table**, on page 20 — being a fairly complete and accurate reference source of useful design information — provides some important design-related conclusions along the way.

### Inductor Current

Inductor current consists of an ac/ramp component (ΔI) and a dc/average component (I_{DC}), the latter being the geometric center of the ramp. For the buck, the average inductor current is the load current. For the boost and buck-boost, the average diode current is the load current. From the **table**:

(Buck)

(Boost/Buck-Boost)

The average inductor current becomes very high if D approaches 1 for the boost and buck-boost. This corresponds to the lowest input voltage (V_{IN_MIN}) for these topologies, and you must conduct the inductor design at this voltage. But for the buck, there's hardly any relationship of inductor design to input voltage, since the average current depends only on the load (which is considered fixed in our analysis). For a buck regulator, we simply pick an inductor with a current rating equal to the load.

We can't ignore the ac component of the inductor current (I_{AC}), defined as the full peak to peak current here, or ΔI — not even for a buck. This parameter is important, because along with I_{DC}, it determines the peak value of the inductor current. This peak value needs to be known so as to accurately evaluate the energy-handling requirement of the inductor (defined as ½×L×I^{2}_{PEAK}). If we don't size the inductor accordingly, the core may saturate. But more importantly, for all topologies, this ac component is completely responsible for the core loss (which doesn't depend on I_{DC}, so long as the inductor isn't saturated).

Now, for all the topologies, there's an applied voltage (V_{ON}) across the inductor when the switch is ON. This causes a certain ac ramp component (ΔI) across the inductor from the basic equation V_{ON}=L×ΔI/(D/f) or ΔI=V_{ON}×D/(L×f), where f is the frequency. As the input voltage falls, V_{ON} also decreases, but D increases. So, what happens to ΔI?

The **table** provides the ΔI term. Here, we can see the following:

(Buck/Buck-Boost)

(Boost)

Plotting these functions out:

ΔI→ maximum at highest input voltage for Buck/Buck-Boost

ΔI→ maximum at V_{IN_50} (or closest voltage) for Boost

Where V_{IN_50}=input voltage at which D=50% for the topology under consideration.

The equation for V_{IN_50} is also provided in the **table**. If the input voltage range doesn't include V_{IN_50}, we must choose V_{IN_MIN} or V_{IN_MAX} — whichever happens to be closer to V_{IN_50}.

We also define a useful parameter called the current ripple ratio r, which is the ratio of the ac to the dc value of the inductor current, with the converter delivering maximum load. So:

(Buck)

(Boost/Buck-Boost)

The parameter (*r*) determines the inductance (L) and the physical size of most of the power components. Increasing *r* reduces the inductor size. However, an *r* of 0.3 to 0.4 represents the most optimum choice for any topology. Allowing greater current ripple than this doesn't appreciably reduce the size of the inductor, but increases the size of the input/output capacitors. Having designed the inductor for a given value of r at the appropriate input voltage end, we vary the input voltage over the expected range, *r* changes accordingly. The equations in the **table** are in terms of *r* and D, the two main parameters that vary with input voltage. Also provided is the variation of *r* with D, making D the only variable in our analysis. You can find the value of the required inductance (based on a chosen *r*) in the **table**, on page 20, and calculate the physical size of this inductor from the required energy handling capability.

### Inductor Energy

Energy handling capability is e=½×L×I^{2}_{PEAK}. This parameter sizes up the inductor for a given application. You don't determine the size only by inductance, since almost any inductance can be theoretically achieved on any core by winding the appropriate number of turns on it. The **table** provides the complete equations for e. For our analysis here, we first make an approximation for the rather complicated term involving *r*. Assuming *r* to be small, this term becomes:

From the **table**, for small *r*, we can see the energy handling capability is:

(Buck)

(Boost)

(Buck-Boost)

Plotting these functions we'll see:

e → constant/maximum at highest input voltage for buck

e → maximum at lowest input voltage for boost/buck-boost

For the boost and buck-boost, required energy handling capability increases as duty cycle approaches 0.6. Such stages are typically of boost topology, providing an internal 400Vdc rail from a worldwide ac input. Size of the inductor goes up as the minimum input voltage falls, so the inductor design should be carried out at the minimum input voltage. For the buck, it doesn't matter if you use the maximum, minimum, or nominal input voltage, provided *r* is as small. The *r* increases as input voltage increases, increasing peak value. Thus, it's preferable to design the buck regulator inductor for the highest input voltage.

### Inductor Current

If *r* is small, the average and rms values of the inductor current are the same (I_{L}). Copper loss in the inductor is I_{L}^{2}×R, where R is the winding resistance. The copper loss is usually large compared to the core loss (which depends on ΔI), and determines the temperature rise of the inductor.

From the **table**, for small *r*, we can see that the rms/Avg current is:

(Buck)

(Boost/Buck-Boost)

For the boost and buck-boost, if D is large, I_{L} increases. Therefore, when evaluating copper loss or temperature rise of the inductor for these, we need to use the minimum input voltage. For the buck, since *r* increases with increasing input voltage, the rms value of the inductor current is also higher, and so we should use the maximum input voltage.

I_{L} → constant/maximum at highest input voltage for buck

I_{L} → maximum at lowest input voltage for boost/buck-boost

### Input Capacitor Current

A key parameter is the rms current (I_{IN}) through the input electrolytic capacitor. It determines the basic/minimum selection criterion since the capacitor must be rated at least for the worst-case rms current that may pass through it. Most manufacturers do not guarantee any specific life for a capacitor operated with an rms current higher than its rated value. Therefore, the provided life expectancy vs. temperature curves/equations may not be valid.

From the **table**, on page 20, for small *r*:

(Buck)

(Boost)

(Buck-Boost)

Plotting these functions out, we see

I_{IN} → maximum at V_{IN_50} (or closest voltage) for buck/boost

I_{IN} → maximum at lowest input voltage for buck-boost

We must also evaluate the temperature of the output capacitor at the above input voltages. If the input voltage range doesn't include V_{IN_50}, we must choose V_{IN_MIN} or V_{IN_MAX}, whichever happens to be closer to V_{IN_50}.

The peak-to-peak current (I_{PP_IN}), through the input capacitor, determines the ripple of the input voltage ΔV_{IN}=I_{PP_IN}×ESR_{IN}, where ESR_{IN} is the equivalent series resistance of the input capacitor. This input ripple is a major component of the EMI spectrum at the input of the power supply.

From the **table**, for small *r*:

(Buck)

(Boost)

(Buck-Boost)

Plotting these functions out we can see the following:

I_{PP_IN} → constant/maximum at highest input voltage for buck

I_{PP_IN} → maximum at highest input voltage for boost

I_{PP_IN} → maximum at lowest input voltage for buck-boost

For a buck stage, the input voltage ripple is almost a constant with respect to input voltage variations, provided *r* is very small. However, since **r** increases at high input voltages, it's preferable to evaluate this parameter at the highest input voltage.

### Output Capacitor Current

The output capacitor value also needs to be at least large enough to handle its worst-case rms current, I_{OUT}.

From the **table**, on page 20, for small *r*, we can see the following:

(Buck)

(Boost/Buck-Boost)

Plotting these functions we can see:

I_{OUT} → maximum at highest input voltage for buck

I_{OUT} → maximum at lowest input voltage for boost/buck-boost

So, the temperature of the output capacitor must also be evaluated at the above input voltages.

We're also concerned with peak-to-peak current (I_{PP_OUT}) through the output capacitor. This determines the output voltage ripple ΔV_{OUT}=I_{PP_OUT}×ESR_{OUT}, where ESR_{OUT} is the equivalent series resistance of the output capacitor. This output ripple is a major component of the noise spectrum at the output of the power supply.

From the **table** for small *r*:

(Buck)

(Boost/Buck-Boost)

Plotting these functions we can see:

I_{PP_OUT} → maximum at highest input voltage for buck

I_{PP_OUT} → maximum at lowest input voltage for boost/buck-boost

In Part 2 (read part 2 now), we'll look at stresses related to the semiconductors and explicitly plot the variation functions referred to in this part. We will then summarize the information in an easy lookup table expressing the correct input voltage for design/test purposes.

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