Power Electronics

Ramp Compensation for Current-Mode Converters

A peak current-mode power supply is subject to subharmonic oscillations if two conditions are met: the converter operates in the continuous conduction mode (CCM) and the duty-cycle is close to or above 50%. When these two conditions occur, the converter produces an oscillation at half the nominal switching frequency. Fig. 1 shows graphically how a perturbation can quickly propagate through the cycles.

The perturbation propagation can be described via a simple formula where IL, the inductor current, is subject to a step ΔIL at t = 0. This step propagates through the cycles according to:

where D represents the duty cycle and “n” is the number of switching cycles. From this equation, we see that if the (D/1-D) quotient is less than 1 (that is, D is less than 50%), then elevated to the power n, the perturbation will naturally die out after a few cycles.

However, if D is greater than 50%, the quotient becomes larger than 1, and the perturbation is carried from cycle to cycle without disappearing. This is the subharmonic oscillation that can be more or less severe depending on the peaking at half the switching frequency. Yes, peaking, like in any tuned filter.

Ray Ridley showed in the 1990s that a current-mode converter was actually a third order converter with a low-frequency pole, ωp, and two poles that are located at Fswitching/2. These poles move in relation to the duty cycle and an external compensation ramp, when present. This artificially created ramp will help to stabilize the power supply. The two high-frequency poles present a Q that depends on this ramp and the duty cycle. Ridley demonstrated that the Q becomes infinite at D = 0.5 with no external ramp (mc = 1), confirming the inherent instability of a CCM current-mode switch-mode power supply operating at a duty cycle greater than 0.5. The quality coefficient Q is defined:

where: mc = 1 + Se/Sn (3)

Se is the external ramp slope (the compensation ramp that you will bring to stabilize the converter), Sn is the inductor on-time slope and D' = 1 - D. For designers, once the system's Q has been determined with Equation 2, they should look for the amount of ramp compensation that will make this number equal to 1:

The ramp either can be subtracted from the feedback signal or added to the inductor current voltage image. This is the most convenient method and one that is widely used.

Stay Away from the Oscillator

In UC384X designs, it's common practice to buffer the timing capacitor saw tooth via a bipolar transistor wired in the common collector configuration. This approach presents several drawbacks. First, the Ct node (pin 4) is a rather high-impedance node because low currents circulate to charge up the capacitor. Therefore, it's not recommended to connect any other elements to this node.

In addition, the Ct voltage swing is around 1.6 V. By inserting a bipolar transistor in series with the capacitor voltage, you subtract a Vbe of 0.65 V @ Tj = 25°C from a 1.6-V swing. That is to say, at high or low junction temperatures, given the -2.2 mV/°C silicon slope, your final ramp amplitude can vary quite a bit and needs compensation somewhere.

The question then becomes how to create a ramp. On modern controllers, the oscillator section is buried inside the circuit, and none of its pertinent signals can be externally accessed. However, you can easily charge a capacitor when the gate drive is high and immediately discharge it when the MOSFET switches off. Fig. 2 shows how to simply generate a saw tooth from the gate drive of an NCP1200 (www.onsemi.com): A resistor, R, charges the capacitor, C, when the gate is high, and this capacitor is brutally discharged via the diode, D, during the off time.

Calculating the RC component values is an easy task because the absolute ramp amplitude doesn't matter, as Rramp will finally be adjusted to cope with our requirements. By drawing a small current from the drive to avoid increasing the dissipated power, R will be of high value. If this is the case, consider this system as a current generator. By applying VC·C=i·t, you calculate R and C.

Suppose we want to create a ramp that goes up to 5 V when a 60-kHz NCP1200 is operating at 50% duty cycle. The on time is:

Let's select a charging current of 500 µA. With a driving gate voltage of 11 V, this leads to a resistor of ≈11 V/500 µA = 22 kΩ. Having a charging current of 500 µA, what capacitor do we need to generate a ramp that reaches 5 V in 8.33 µs?

or 820 pF for the normalized value. A quick SPICE simulation confirms our assumptions with a peak ramp value of 4.5 V or a sweep of 4.5/8.33 u = 540 mV/µs (Sramp).

The next consideration is the compensation level to be injected. Based on equation 4, suppose we need an mc of 2.2. Via equation 3, we can calculate the slope of the necessary ramp:

Assume we build a flyback converter featuring a 1-mH primary inductance Lp operated from a 120-Vdc input voltage. The sense element is a 0.5-Ω resistor. Our primary Sn slope, reflected over Rsense, is then: (120/1m) × 0.5 = 60 mV/µs. Therefore, from equation 5, we can calculate Se: (2.2 - 1) × 60 = 72 mV/µs. Compared to Sn (60 mV/µs), it is a ratio M of 72/60 = 1.2.

The final resistor value is computed by freezing R2, 3.3 kΩ for example, and finding Rramp using:

Rramp = R2 × Sramp / (Sn × M) = 3.3 × 0.54/(0.060 × 1.2) = 24.7 kΩ.

Note that a 24.7 kΩ + 3.3 kΩ combination will load the ramp generator, which has a 22-kΩ output impedance. Thus, tweak the prototype to account for this loading effect.

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