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The phase-shifted full bridge with current doubler output stage is a popular power supply topology in high-power and low-voltage, high-current applications that demand high efficiency. A power supply using the converter's ZVS (zero voltage switching) characteristics — along with synchronous rectification on the output stage — can achieve efficiencies of more than 90%. However, driving a current doubler synchronous rectification output stage can be complex, especially for a phase-shifted full bridge topology.
Understanding the synchronous rectifier switching requirements requires some background in phase-shifted timing fundamentals. In Fig. 1, the full bridge comprises four primary side MOSFET devices labeled QA, QB, QC, and QD. Power is transferred to the transformer secondary whenever any two diagonal switches, QA and QD or QC and QB, are on simultaneously. Conversely, whenever the two upper or lower switches, QA and QC or QB and QD, are on simultaneously, this is called the freewheel state. During the freewheel state, the transformer primary is shorted, resulting in zero voltage across the primary and secondary windings. Also, though not shown in the timing diagram of Fig. 1, there is a finite delay between the turn off and turn on of QA and QB and QC and QD, when the resonant period occurs.
Neglecting delay times, four distinct switching states make up one full switch cycle of the phase-shifted full bridge.
QA and QD are on, causing a positive voltage to appear across the transformer secondary dotted end. This corresponds to Q2 being on and Q1 being off, providing two separate current paths through L1 and L2. The transformer secondary current is equal to the current through L1, which is half the total output current. The second half of the output current is delivered via L2 freewheeling through Q2. Q2 is carrying the full load current during this state.
QA and QC are on, causing the voltage across the transformer, VT, to be zero. On the secondary side, Q1 and Q2 are on as well. The current in L2 has the same slope as the previous t0→t1 state, while the current in L1 has changed to a negative slope due to the voltage across L1 also becoming negative. L1 and L2 are now freewheeling. Because there's zero voltage across the transformer, the magnetizing current, IM, doesn't change in this state.
QC and QB are on, causing a negative voltage to appear across the transformer secondary dotted end. This corresponds to Q1 being on and Q2 being off. The transformer secondary current is equal to the current through L2, which is half the total output current. The second half of the output current is delivered via L1 freewheeling through Q1. Q1 carries the full load current during this state.
t3→t4 = t0:
QB and QD are on, causing the voltage across the transformer, VT, to be zero. On the secondary side, Q1 and Q2 are also both on. The current in L1 has the same slope as the previous t2→t3 state, while the current in L2 has changed to a negative slope due to the voltage across L2 also becoming negative. Both L1 and L2 are now freewheeling. Similar to state t1→t2, since the transformer voltage, VT is again zero, the magnetizing current, IM, doesn't change during this state.
Traditionally, synchronous rectifiers are either self-driven directly from the transformer secondary voltage or control-driven, where the desired gate drive signals are derived from the PWM controller. Since part of the phase-shifted full bridge switching cycle contains a freewheel period, as noted in states t1→t2 and t3→t4 of Fig. 1, on page 52, there's no transformer voltage available for the synchronous rectifier gate drives during this period. Therefore, self-driven synchronous rectification isn't an option with this topology. This brings attention to control-driven synchronous rectification.
By observing each of the four switching states in Fig. 1, the truth table in Fig. 2 and its corresponding logic circuit can be established, defining the relationship between the PWM control signals and the synchronous rectifiers.
The circuit in Fig. 2 is an example of primary side PWM control, where the NAND gates handle all of the PWM demodulation before passing the synchronous rectifier drive signals through a signal transformer and onto a secondary side referenced driver circuit. The problem with this approach is the excess amount of signal delay taken on by the additional logic gates. Because the turn-off of the appropriate synchronous rectifier must precede the start of the next primary side switching command, some delay is acceptable. However, too much delay can result in either of the synchronous rectifiers staying on during the start of the next switching state, where the corresponding command would otherwise be to turn off the switch.
Realizing the problems associated with externally developing the synchronous rectifier drive signals, some newer controllers include this logic internally. Although this may seem like a convenient feature, a compromise is realized by the additional requirement of two IC pins and silicon area, along with higher PWM cost.
There is a simple way to drive the synchronous rectifiers of a phase-shifted full bridge without incurring any of these problems. Referring back to Fig. 1, note that the current flowing in the secondary during the t1→t2 state is almost identical to the secondary current flow shown in the t0→t1 state. If Q1 were not turned on during the t1→t2 state, then the corresponding gate drive signal GATE 1 would be identical to GATE B.
Similarly, the current flowing in the secondary during the t3→t4 state is almost identical to the secondary current flow shown in the t2→t3 state. If Q2 were not turned on during the t3→t4 state, then the corresponding gate drive signal GATE 2 would be identical to GATE A. The timing diagram in Fig. 3 highlights the implications of using the primary referenced PWM signals, GATE A, and GATE B to directly drive the synchronous rectifiers.
Comparing the timing diagram of Fig. 3 to that of Fig. 1, the only difference occurs during the freewheel period, highlighted in Fig. 3. During the freewheel period in Fig. 1, both output rectifiers are conducting. Conversely, during the same period in Fig. 3, only one of the synchronous rectifiers is conducting. Because the current flowing during the freewheel state remains in the same rectifier as the previous state, the switching action — as far as the output load current is concerned — will remain unchanged, as shown in Figs. 1 and 3.
What about body diode conduction between the interval of Q2 turning off and Q1 turning on or vice versa? Typically, there's a dead time associated between the turn off of one synchronous rectifier and the turn on of the alternate rectifier, as might be expected between the t1→t2 and t3→t4 intervals. During this dead time, the circulating current would normally be forced to flow through the synchronous rectifier body diode. However, unique to the phase-shifted full bridge topology is the freewheel period where the transformer primary is clamped. Clamping the transformer primary results in 0V across the primary — and thus 0V across the secondary. With 0V across the transformer and no change in the magnetizing current, body diode conduction in the synchronous rectifiers is virtually eliminated.
Driving the synchronous rectifiers directly with the GATE A and GATE B PWM signals removes the logic circuitry previously shown in Fig. 2. The propagation delays mentioned are also eliminated. Using this technique, the synchronous rectifier Truth Table and corresponding gate drive circuit are now reduced to that of Fig. 4.
Fig. 5 shows a simplified application diagram, using the AB signals from a phase-shifted full bridge PWM controller to drive the synchronous rectifiers of a current doubler output stage. While this technique can be applied to any phase shift controller, the UCC3895 is featured in this application. By not including the logic circuitry shown in Fig. 2, the UCC3895 can free up two additional IC pins. The additional pins are utilized by offering more advanced features such as ADS (Adaptive Delay Set), which is used to extend the converter's ZVS load range while maintaining the maximum possible duty cycle range. The UCC3895 also offers separate power and signal ground pins, assuring reliable noise-free operation within the IC.
Also shown are the UCC37324 MOSFET drivers. These dual 4A drivers are recommended for high-frequency designs where high speed, high peak current, and minimal rise and fall times are necessary. For additional support, there's the UCC3895EVM-001 evaluation module.
The UCC3895EVM-001 uses the AB outputs of the UCC3895 for direct control driven synchronous rectification of a current doubler output stage, helping the user to better understand this novel switching technique.
Balogh, L. Design Review: 100W, 400 kHz, DC-DC Converter With Current Doubler Synchronous Rectification Achieves 92% Efficiency, Topic 2, SEM-1100 Power Supply Design Seminar Manual, Texas Instruments/Unitrode Corp., Literature Number SLUP111.
Balogh, L. The Current Doubler Rectifier: An Alternative Rectification Technique For Push-Pull and Bridge Converters, Texas Instruments Application Note SLUA121.
UCC3895 Data Sheet, Texas Instruments.
UCC37324 Data Sheet, Texas Instruments Literature Number SLUS492B.
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