Power Electronics

PWM Controller IC Simplifies Telecom Distributed DC-DC Converter Designs

High-voltage, high-speed telecom dc-dc converter controller IC

Today's telecom and data communication networks require efficient, high-density dc-dc solutions for converting the -48Vdc bus to low-voltage, high-current outputs. Output voltages range from 1.5Vdc to 5Vdc — with typical outputs ranging from 10A to 30A in half-brick to quarter-brick sizes and smaller.

One efficient telecom dc-dc converter approach uses the MIC9131 PWM controller IC, a switchmode, resonant reset, forward converter with synchronous rectification that can develop a 3.3V, 20A output from a -48Vdc bus. This topology has a simplified transformer design, and it easily adapts to secondary side synchronous rectification.

In quarter-brick applications, limitations on the p. c. board size are 1.45 × 2.3-in., with component height limited to 0.32-in. on the top side and 0.07-in. on the bottom side for a total height of 0.452-in. — including the board thickness. The MIC9131's 16-pin narrow-body SOP and minimized parts requirements enables the packaging of a quarter-brick converter within these constraints. This controller (Fig. 1) has features essential to achieving the optimum efficiency and density for this type of converter. You can program its clock speed to 2.5 MHz, or synchronized to 4 MHz, which gives it a maximum switching capability of 500 kHz or 1 MHz, respectively, enabling use of a smaller transformer and output filter. It allows a maximum duty cycle of 75%, which allows a greater transformer turns ratio, thus a lower primary current and reduced losses.

Another version, the MIC9130, allows a 50% maximum duty cycle. Both versions have integrated start up circuitry, eliminating the need for a start up resistor or additional external start up circuitry, which can use up valuable p. c. board space and add to increased power loss. Other integrated features include undervoltage lockout (UVLO), enable/disable, external sync, and a current limit initiated soft start option.


With a typical dc-dc converter, start up, line-detect turn on, and turn off circuitry can take some time to develop, and it consumes p. c. board area. In contrast, the MIC9131 integrates most of these functions, requiring only a simple resistive divider at the UVLO pin to set the turn on voltage. Hystersis built into the UVLO comparator prevents the circuit from toggling on or off in the presence of noise and/or a high input line impedance.

Fig. 2, on page 16, shows the startup circuit. Power to the chip is regulated internally during start up. The MIC9131 line input is rated up to 180Vdc, allowing direct connection to the -48V input. This input develops Vcc at start up until the bootstrap winding takes over, disabling the internal depletion mode MOSFET. The IC disables the depletion mode MOSFET when Vcc reaches 8.7Vdc. It enables the depletion MOSFET if Vcc drops below 7.9Vdc. Once the bootstrap winding forces the Vcc above 8.7Vdc the depletion MOSFET remains disabled.

Feeding the bootstrap winding off the output inductor provides a constant Vcc with respect to line. Vcc is regulated internally during start up, so you can use a smaller value Vcc “hold-up” capacitor than would have been necessary otherwise. The depletion mode MOSFET also takes over once the bootstrap winding goes to zero during a short circuit. Tying the CPWR pin to the VBIAS rail resets the soft start capacitor during current limit and limits short circuit current.

Current Mode Control

In this design, you use peak current mode control with isolated voltage feedback provided by an optoisolator. You can use a transformer or less efficient, lower-cost resistor to sense current. The ISNS pin sources 50μA; if desired, you can use it to reduce the value of the sense resistor to improve efficiency. A resistor in series with ISNS (R21), as shown in Fig. 3, provides a dc offset equal to the ISNS source current (50μA) times the resistor value. This offset is added to the sensed current and reduces the size of the current sense resistor and its associated losses.

The MIC9131's programmable oscillator is four times the converter switching frequency. Because of this, you can't use it to develop a slope compensation signal. However, Figs. 3 and 4 show the method used to adapt the MIC9131 for current mode operation with slope compensation. The slope compensation signal is a ramp developed by the RC network (R24 and CR5) tied to the VBIAS pin. A cleaner ramp was possible when charging C21 from the VBIAS output, as opposed to charging it directly from the OUT pin of the MIC9131. The ramp is discharged at the end of the on-time via a diode (CR5) tied to the OUT gate drive pin. An additional diode (CR7) compensates for the offset in the discharge diode (CR5). R21 and R23 adjust the slope compensation magnitude and sum the compensation signal with the sensed signal.

The loss-less snubber in Fig. 5 provides the transformer reset. With this reset scheme, you can modify C9 with little impact on efficiency, and you can obtain a reset voltage sufficient for a 75% maximum duty cycle (MIC9131).

Synchronous Rectification

Two different methods of synchronous rectification provide good efficiency results. The first method is the simplest, but it requires an additional Shottky diode, as shown in Fig. 6, on page 18. The Shottky (CR1) takes on the freewheeling current of the main inductor once MOSFETs Q3 and Q5 lose their gate drive. This happens once the transformer primary collapses to zero after reset. You can select the snubber capacitor C9 (Fig. 5, on page 18) to minimize this effect, but it won't eliminate the need for the Schottky diode.

The second method (Fig. 7) doesn't require the additional Shottky diode, but needs an additional transformer winding. This keeps transistors Q3 and Q5 on during the entire off-time — regardless of the transformer primary voltage. The gates of Q3 and Q5 peak-detect the voltage on the gate drive winding. Small signal MOSFET (Q6) then discharges the gate voltage at the beginning of the next clock cycle.

Q6 must be sufficiently fast to prevent any significant simultaneous conduction of Q3 and Q5 with Q2 and Q4 at the beginning of the cycle. Figs. 8 and 9, on page 20, display some typical waveforms for this configuration.


Using planar type E18/4/10 3F3 ferrite cores for the transformer and inductor, the transformer secondary and inductor were wound with copper foil. For optimum coupling, the transformer primary is 12 turns sandwiched in the two turns of the secondary foil. The inductor value was chosen for ripple current of 20% of the full load current.

Fig. 10 displays the measured efficiency of a typical dc to dc converter using the MIC9131. The transformer and inductor design was critical in meeting the desired efficiency and current capability. Close work with Transpower Technologies (775-852-0140) helped significantly to this end. The features with the greatest impact on efficiency were the output choke design, synchronous rectification, and the MIC9131's 75% maximum duty cycle capability.

Room temperature current capability with no airflow was about 13Adc with the synchronous rectifiers being the limiting devices. A more optimum placement of these devices is expected to improve this rating.

The quarter-brick sized p. c. board provided more than enough room for component placement. The integrated start-up and line detect circuitry freed up a significant amount of board area. Only roughly half of the bottom side of the board containing the control circuitry was used. Total required board space was about 5.5 in2.

Fully functional assemblies will be available as an evaluation board for the MIC9131. At that time, full characterization of the ripple, regulation, and transient response characteristics will be available.


Xie Xuefei, Joe C. P. Liu, Franki N. K. Poon, Bryan M. H. Pong, “Two Methods to Drive Synchronous Rectifiers During Dead Time in Forward Topoligies,” APEC 2000 Conference Proceedings, pp. 993-999.

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