Radical changes in the implementation of distributed power in high-power, high-reliability applications are now taking place. Instead of the conventional approach of busing individual voltages on an elaborate backplane, there's a move to multiple point-of-load power supplies, each developing the multiple, on-card voltages. Along with newer distributed power architectures, this will eliminate multiple high-current bus bars in exchange for a single 24V to 48V distributed dc source.
This new power conversion technique incorporates a cascaded arrangement of a push-pull converter using synchronous rectification followed by a buck regulator, also using synchronous rectification, as shown in Fig. 1. However, there are numerous differences between this adaptation and the conventional versions of both converters. The list of advantages includes zero voltage switching of the push-pull converter switches and rectifiers and near-lossless turn-on of the buck regulator switch. Strategically located transformer leakage inductance, present on the secondary side, defines the rate of change in current (dI/dt) at turn-off of the buck's commutation rectifier switch. Each contributes to developing a power management solution with higher overall efficiency and lower EMI/RFI. Complete circuit details are available including voltage, current, and timing waveforms [1,2].
The push-pull converter runs continuously at about a 50/50 duty cycle at each switch, using virtually all the available conversion cycle for processing power. Incorporated in the circuit is a small amount of deliberate off-time (dead-time) prior to activation of the opposite switch, which facilitates lossless zero voltage switching (ZVS) of the primary switches, Q1 and Q2. Once you turn a switch off, the established magnetizing current of the transformer's primary inductance propels the opposite transistor's drain voltage to reach zero volts every switching cycle. The circuit's stored and opposing energy requirements determine the exact off-time, as defined by the values of the magnetizing current, MOSFET output capacitance, transformer and parasitic circuit capacitance, and input supply voltage [3,4].
On the secondary side of the transformer, note the particular detail regarding the transformer's windings and connections — especially the center-tap. The utility of this configuration is that both synchronous rectifiers are ground referenced, thus simplifying the gate drives. When using a secondary-side referenced control circuit, you can drive the primary side switches from isolated versions of the gate drives to Q1' and Q2'. Since the duty cycle involved is constant, a simple transformer coupled circuit suffices for either variety.
Further differences between this cascaded adaptation and conventional approaches are also evident in the buck regulator section. There is no output filter inductor or capacitor between the secondary side of the transformer and the input to the buck regulator. Therefore, a pulse-train comprised of the rectified secondary voltage rather than a more normal dc voltage feeds the buck stage. Although somewhat unconventional, this technique works quite advantageously, given the right control circuitry. Make sure you pay particular attention to the simplicity of this configuration when generating multiple outputs. The design of the transformer's turns ratio supplies the secondary with the highest output voltage required. You can derive all other lower output voltages separately, using buck regulators from the same output node. It requires no additional secondary windings, filter stages, or push-pull synchronous rectifiers. Fig. 2 illustrates the PWM control waveforms.
Combining a control strategy with low-loss switching, the buck regulator switch turns off coincident with each switching cycle and the collapse of the rectified transformer secondary voltage. This technique implements “leading edge modulation” as opposed to the traditional PWM technique of “trailing edge modulation.” The circuit forces synchronization of the buck control circuit to the main converter, coinciding with turn-off of the push-pull converter switches. Turn-on of the buck's forward switch is nearly lossless due to the finite leakage inductance of the transformer's secondary winding. You can extract the buck's commutating synchronous rectifier gate drive from the gate driver ICs in the PWM control circuit.
The overwhelming majority of PWM controllers regulate a single power supply output and are therefore unlikely to house all of the decoding logic required to implement the numerous gate drive signals for multiple output applications. You can configure any alternating, dual output PWM to address the fixed frequency, 50/50 duty cycle gate drives needed for the push-pull section.
There's a limited selection of leading-edge modulation PWMs for the buck regulator referred to as “secondary-side post regulator” controllers. The UCC3583 controller addresses this application (Fig. 3, on page 30). The uniqueness of this controller is its internal architecture has the logic reversed in contrast to standard conventions.
The ability to synchronize to the trailing edge of the push-pull converter's pulse train is necessary.
Although intended for controlling zero voltage transition full bridge converters, you can use one PWM for this application to derive both the push-pull outputs and main buck regulator output. The UCC3895 PWM controller features four outputs labeled A, B, C, and D arranged as two pairs (A/B and C/D) of half-bridge drivers for driving the four switches of a full-bridge converter (see Fig. 4, on page 32). Each output within the pairs alternately switches at about 50% duty cycle with programmable dead time.
The second set of half-bridge drivers, outputs C and D, are phase shifted, with respect to the output pair A and B. As the error amplifier commands a wider output voltage, it increases the phase shift between outputs A/B and C/D. This lengthens the simultaneous on-time of the diagonal switches in the full bridge converter, thus widening the delivered duty cycle to the secondary. This can achieve true zero duty cycle to nearly 100% duty cycle.
Implementation of the control strategy incorporates an unconventional use of the IC's four PWM outputs to achieve the desired three commands for the push-pull and buck gate drives. Since two pairs of IC outputs are switching at nearly 50/50 duty cycle each, obtaining the command signals for the push-pull is straightforward. However, extracting the effective duty cycle for use in the buck stage signal requires minor gating of the four PWM outputs using standard digital logic gates (Fig. 5, on page 34). Logically ANDing output A with D on one clock cycle, and ANDing output B with C for the next switching cycle deciphers the duty cycle. Logically ORing these two pulse trains together produces a cycle-by-cycle pulse width signal to drive the buck's switch. The specific circuit implementation uses NAND gates instead of AND and OR logic for simplicity.
This technique uses a generated sync pulse throughout the complete control for this multiple output application. Fig. 6, on page 34, shows the converter's fundamental timing waveforms. You must use outputs C and D for the push-pull to achieve the desired leading-edge modulation of the buck regulator, with respect to the push-pull converter's timing cycles.
The UCC3583 secondary side PWM controllers regulate all additional switchmode outputs beyond the first one. This uses the IC in an unconventional configuration in comparison to its intended use. Internally tied to the non-inverting input of the IC's voltage error amplifier is one-half the reference voltage, or 2.5V. The IC has a programmable current amplifier to provide an overcurrent limiting function. The outputs of both amplifiers along with the soft-start function connect to the PWM ramp comparator inverting input. These ORing diodes allow an override of the other two inputs by any one amplifier or function commanding a narrower duty cycle. A “high” amplifier output produces a zero duty cycle and a “low” amplifier output commands a full duty cycle. This inversion respects most conventional PWMs, but the same is true for the timing capacitor waveform used as the positive input to the PWM comparator, or ramp. The cycle begins with the capacitor charged to its upper threshold and is linearly discharged during the remainder of the switching cycle. Therefore, an external op amp inverts the output voltage feedback signal fed to the IC's error amplifier.
Incorporated in the voltage feedback and overcurrent circuitry is a 2V reference threshold that minimizes the number of necessary passive components. For output voltages above 2V, a simple resistor divider network from the output voltage to ground is input to the external error amplifier inverting input. For output voltages below 2V, a resistor divider network from VOUT to the IC's reference voltage increases the feedback voltage to 2V. Outputs greater than 2V populate resistor locations RV2 and RV3 whereas sub 2V outputs use resistors RV1 and RV3.
The same biasing principles apply to the current amplifier used to provide overcurrent limiting. It has a maximum input common mode specification of 2V, so you probably need resistor divider networks either to ground or VREF, depending on the output voltage. A differential current sensing technique across the current sense resistor achieves enhanced current limiting. The output voltage develops a portion of the current amplifier's voltage threshold set at ILIM. Avoid using a divider directly from VREF to ground, as this will not provide protection should the output voltage drop — as in the case of most overcurrent faults.
There are several ways to synchronize the UCC3583 buck PWM controllers. The simplest technique is to divide down the output of the push-pull synchronous rectifier waveform, forcing synchronization to the beginning of each switching cycle. In this example, the UCC3895 PWM develops the synchronization pulse and buses it to the UCC3583 buck PWM stages.
You can control exact timing between turn-off of the buck switch and turn-on of the push-pull's next switching cycle using the UCC3895 C-D Delay function. This delay circuitry serves three purposes in this application. First, it sets the delay time to match the resonant transitions of the push-pull gate drive to the exact resonant tank timing. Second, it defines the maximum duty cycle of the UCC3895 controlled Buck regulator. Finally, you can use the C-D Delay function to delay the turn-on of the next push-pull switching cycle to match actual circuit and propagation delays in the UCC3583 controlled auxiliary buck stages. Empirical measurements of the buck's gate drive and drain current determine the best delay to yield higher efficiency.
You can obtain higher efficiency multiple outputs by converting the buck regulator power stages to incorporate synchronous rectification. High current gate drive ICs with internal decoding logic drive both switches from a single input, such as the TPS2813 dual complementary driver. Featuring a peak output current of 2A, this device also has crisp transitions of 15 ns and brief propagation delays of 25 ns in each buck.
Proper signal timing is critical — especially in synchronous rectifier drive applications. There should be no overlap between the complementary gate drives, and there should be sufficient time for complete removal of the gate charge before activating the opposing synchronous switch. You can implement this by adding a delay to the turn-on of each switch. However, in this zero voltage switching application, the bigger concern is turning on the forward buck switch before turning off the commutating switch channel. In one implementation, add a brief delay only to the turn-on of the forward buck switch. We chose an arbitrary 68 ns time constant for this example. To do this, insert a series RC network of 68 pF and 1kΩ between the UCC3583 output and the TPS2813 gate driver IC. To keep this delay from affecting the quick turn-off of the forward buck switch, place a diode in parallel with the resistor, which prevents a delay in the turn-off command. You can later optimize this initial 68 ns time constant for each buck regulator's gate drive based on empirical results and efficiency measurements. Fig. 7, on page 34, shows the associated waveforms for the second buck output. The delay is applicable to output 3 as well.
Fig. 8 shows the complete circuit schematic of the buck stages, gating logic, and driver ICs, while Fig. 9 shows three buck regulators operating at different duty cycles and corresponding to different output voltages. Fig. 10 demonstrates the second and third buck stages ability to fully maintain regulation with the main buck running at zero duty cycle.
Previous design efforts of an isolated 48V to 1.5V at 20A single output version of this technique resulted in an overall efficiency of 80.5% at half load and 78% at full load while operating at 500 kHz. Future development using this control strategy will include the design of a 48V input to a three low-voltage output converter.
Balogh, Bridge and Andreycak, Texas Instruments/Unitrode Power Supply Design Seminar, SEM-1300, Topic 1, “Unique Cascaded Power Converter Topology for High-Current Low-Output Voltage Applications,” 1999, Texas Instruments Publication No. SLUP002.
Balogh, Bridge and Andreycak, US Patent No. 6,246,592, “Unique Power Supply Architecture with Cascaded Converters for Large Input-to-Output Step-Down Ratio,” Assigned June 12, 2001 to Texas Instruments Inc.
Andreycak, Texas Instruments/Unitrode Application Note No. U-136A, “Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM Controller.”
Balogh, Texas Instruments/Unitrode Power Supply Design Seminar, SEM-1100, Topic 2, “Design Review: 100W, 400 kHz, DC/DC Converter with Current Doubler Synchronous Rectification Achieves 92% Efficiency,” 1996, Texas Instruments Inc.