Power Electronics

POWER electronics PATENTS


Issued July 14, 2009
United States Patent 7,560,909

Power converters employing extrapolative-conductance-mode (ECM) control utilize periodic current sampling and employ an extrapolation method to determine charge pulse duration. In preferred embodiments, the operating frequency of the converter is altered in response to current-sample perturbations to dissipate sub-harmonic oscillations associated with duty cycles of 50% or greater without the use of slope correction. High-current-monitor signal-to-noise ratios may be achieved in conjunction with low power losses, and a first order output-filter response may be obtained for duty cycles greater than 50%.

Inventors: Coleman; Edward P. (Salt Springs, FL)

Assignee: Asahi Kasei Microsystems Co., Ltd. (Tokyo, JP)

Appl. No.: 11/273,452

Filed: November 14, 2005


Issued July 14, 2009
United States Patent 7,560,945

An integrated circuit, having a frequency generator connected to a constant reference-voltage source located on the IC and a monitor connected to monitor the frequency signal, [uses] the frequency history to predict that an IC failure will occur. An adaptive power supply is disclosed that includes a frequency generator connected to a band-gap voltage source and is monitored for changes in the frequency-generator output. From this change a prediction is made as to a failure condition that will occur.

Inventors: Singh; Deepak K. (Apex, NC)

Assignee: International Business Machines Corporation (Armonk, NY)

Appl. No.: 11/671,599

Filed: February 6, 2007


Issued July 14, 2009
United States Patent 7,561,425

An apparatus and method for cooling electronics is disclosed. An encapsulated inert non-conductive fluid is used to transfer heat directly from an electrical circuit — including a die on a substrate to an external heat sink. The top of a flip-chip die (e.g. a ceramic column grid array flip chip) may be enclosed with a metallic cover. The metallic cover is sealed to an outer frame, which in turn is sealed to metallization on the top of the flip chip through a flexure, minimizing mechanical load imparted to the flip chip. This forms a hermetic cavity enclosing the die. This hermetic cavity is partially filled with an inert non-conductive fluid which vaporizes when heated. Condensation occurs on the inner surface of the metal cover where the heat may be conducted into the outer frame for removal (e.g. rejection from the spacecraft).

Inventors: Mindock; Eric S. (Playa del Rey, CA), Scott; John R. (Torrance, CA)

Assignee: The Boeing Company (Chicago, IL)

Appl. No.: 11/422,730

Filed: June 7, 2006


Issued July 14, 2009
United States Patent 7,561,408

A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.

Inventors: Pezzani; Robert (Vouvray, FR)

Assignee: STMicroelectronics S.A. (Montrouge, FR)

Appl. No.: 10/727,189

Filed: December 3, 2003


Issued July 14, 2009
United States Patent 7,561,446

A transformer-coupled buck-boost dc-dc power converter is disclosed. An active clamp circuit is provided to form a resonant circuit with the transformer to control the slew rate of the secondary current and allow the secondary switch to be turned ON at conditions of zero voltage and relatively low current. The characteristic resonant period of the active clamp transformer circuit may be less than the minimum converter operating period. A winding of the transformer is shunted during a clamp phase to retain energy in the transformer. ZVS phases are provided to reduce switching losses when switches in the converter are turned ON. An energy-storage phase may be varied to control the amount of energy stored per operating cycle. An input-storage phase may transfer energy to the clamp capacitor during a series of converter operating cycles and transfer said energy to the secondary during different converter operating cycles.

Inventors: Vinciarelli; Patrizio (Boston, MA)

Assignee: VLT, Inc. (Sunnyvale, CA)

Appl. No.: 11/228,068

Filed: September 15, 2005


Issued July 14, 2009
United States Patent RE40,843

A dimmable electronic ballast for an HID lamp includes a rectifier stage for rectifying an ac input and providing a rectified dc output; a power-factor-correction stage for modifying a power factor of the ac input and for providing an increased-voltage dc output from the rectified dc output; an electronic ballast control circuit for providing a driving signal comprising a pulse train for controlling a switching operation of an output switch stage driving the HID lamp, the output switch stage having at least one electronic switching element coupled to the increased-voltage dc output for providing a pulsed power signal to the HID lamp to power the lamp, the electronic ballast control circuit having a feedback input comprising a signal related to the power dissipated by the HID lamp for maintaining the power at a desired level, the desired level being set by a dimming control input to the electronic ballast control circuit. The circuit provides high-frequency power, typically above 50 kHz, to the HID lamp.

Inventors: Ribarich; Thomas J. (Laguna Beach, CA)

Assignee: International Rectifier Corporation (El Segundo, CA)

Appl. No.: 11/262,564

Filed: October 28, 2005


Issued July 14, 2009
United States Patent 7,561,451

In a power-converter apparatus, such as an uninterruptible power supply, a phase reference signal is generated responsive to a dc voltage on a dc bus. A magnitude reference signal may be generated responsive to a phase current of an ac bus and/or the dc voltage on the dc bus. Power is transferred between the ac and dc busses responsive to the phase reference signal and the magnitude reference signal. Generation of the phase reference signal may include generating a dc voltage error signal responsive to the dc voltage on the dc bus, generating a phase offset signal responsive to the dc voltage error signal, and generating the phase-reference signal responsive to the phase offset signal. Generation of the magnitude reference signal may include generating a volt-amperes-reactive (VAR) error signal responsive to the phase current and generating the magnitude reference signal responsive to the VAR error signal.

Inventors: Tracy; John G. (Raleigh, NC), Pfitzer; Hans-Erik (Wake Forest, NC), Bauman; Keith (Oxford, NC)

Assignee: Eaton Corporation (Cleveland, OH)

Appl. No.: 10/834,696

Filed: April 29, 2004

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