Power Electronics Power Conversion Synthesis Part 2: Zero Ripple Converters

Let's look at how to extend the new synthesis methods to achieve converters with zero ripple.

By simply extending the synthesis method, you can achieve three terminal networks with zero ripple for all three terminals — which might be considered a true near-zero emissions topology. Looking at Fig. 1, you can see how adding two switches, S3 and S4, creates a voltage waveform that's 180° out of phase from the waveform created by two original buck switches, S1 and S2. Capacitor C1 is placed in series with L2, so the current in L2 is ac, and the dc voltage at the terminals of L2 is the output voltage. Output voltage for the buck converter is given by its transfer function VO = d × VI, where VO is the output voltage, d is the duty cycle of switch S1, and VI is the input voltage. We can apply Faraday's Law to L2 to assert that in the steady state, the sum of the volt second products applied to L2 over a full cycle is zero, (-VO — VC1) × d × T + (VI — VC1 — V0) × (1-d) × T = 0, where VC1 is the capacitor C1 voltage and T is the period, which we can solve for VC1, using the transfer function, to get VC1 = VI — 2 × V0.

Let's assume that L1 and L2 are uncoupled and that their inductances, L, are equal. During the on time of switches S1 and S4 the current slope for L1 is

The current slope for L2 is

The current slopes are equal in magnitude but of opposite sign, thus the net current slope at the output terminal, which is the sum of the current slopes of L1 and L2, is zero. We'll leave it to you to show that the output current slope is zero during the on time of the switches S2 and S3.

Key point No. 1: If two inductors are connected to a common terminal and ac voltages are applied to the inductors such that the current slopes in the inductors are equal in magnitude and opposite in direction, then the net current slope of the two inductor combination at their common terminal is zero.

Key point No. 3 of Part 1 of this article series asserts that L1 and L2 can be combined on a common core if their windings have equal turns. The Fig. 1 circuit achieves zero ripple at the output terminal, but the input terminal current is pulsating. Another shortcoming of this circuit is that two additional switches are necessary to achieve zero output ripple. One problem with zero ripple circuits is the load transient response is compromised, due to the low net current slope. Following up with Reference 1 provides you with a solution for this problem in the Fig. 1 circuit.

Common mode noise can result from displacement currents in parasitic capacitances at the high dV/dt circuit nodes if the plates of the parasitic capacitance are on opposite sides of an isolation boundary. Displacement current can be expressed as ICM = CPARA × dV/dt, where ICM is the displacement current and CPARA is the parasitic capacitance of the high dV/dt circuit node. In Fig. 1, nodes A, B, and C are nodes with high dV/dt, but the waveform for node A is out of phase from the waveforms at nodes B and C, so there's a degree of displacement current noise cancellation. The amount of noise cancellation depends on parasitic capacitances at the circuit nodes with high dV/dt. A neutralizing capacitor(s) can be added to this circuit to obtain more complete noise cancellation.

Synthesis of Converters

Fig. 2 illustrates a buck converter whose synthesis was described in detail in Part 1 of this article series . This circuit achieves nonpulsating terminal currents at all three terminals and displacement current noise cancellation. Based on key point No. 1, the circuit in this figure can be modified to achieve ripple current cancellation at all three terminals. The process is similar to the process whereby the buck converter is modified to achieve the Fig. 1 circuit. To achieve ripple current cancellation at each terminal, we need to add a second winding at each terminal.

We must connect the second winding to an ac source that provides a current slope in the second winding that's equal in magnitude and opposite in direction to the current slope in the first winding. In the circuit from Fig. 2, we already have ac voltages that are equal in magnitude and opposite in direction without the addition of any new switches. Compare ac voltages at nodes A and C. When switch S1 is turned on, the node A voltage falls and the node C voltage rises. When switch S2 is turned on, the node A voltage rises and the node C voltage falls. The magnitudes of the ac voltages at nodes A and C will be equal if each winding has the same number of turns.

Fig. 3 illustrates a circuit, based on the Fig. 2 circuit, that adds the second windings at each terminal needed to achieve ripple current cancellation. Each second winding is connected to an ac voltage that provides the proper phase to achieve the desired cancellation. Note: The ac voltages at nodes A, B, and C are in phase with each other, and the ac voltages at nodes D, E, and F are also in phase with each other, but out of phase from nodes A, B, and C. Also, only dotted terminals are connected to nodes A, B, and C and only undotted terminals to nodes D, E, and F. Capacitors provide for proper dc voltages at each winding. The capacitors guarantee that no dc current will flow in any of the second windings. In Fig. 3, the voltage applied to capacitors CY1 and CY2 is the output voltage. The voltage applied to the CX1 and CX2 capacitors is equal to the input voltage minus the output voltage, as can be determined by applying key point No. 5 from Part 1 of this article series. Wave forms for the Fig. 3 circuit are illustrated in Fig. 4, on page 56.

The magnitudes of the high dV/dt generators in the Fig. 2 and Fig. 3 circuits are half of the magnitudes of the high dV/dt generators in the Fig. 1 circuit. These dV/dt magnitudes are derived for Fig. 2 in Part 1 of this article series. There is also a high degree of balance in the Fig. 3 circuit that impacts the parasitic capacitances. Nodes A, B, and C are connected to one switch positive terminal, one switch negative terminal, three winding terminals, and four capacitor terminals. Nodes D, E, and F have exactly the same set of connection types, so the parasitic capacitances can be expected to be, if not equal, at least close to equal. If the parasitic capacitances at nodes A, B, and C are equal to the parasitic capacitances at nodes D, E, and F, then displacement current cancellation will be relatively complete. If the parasitic capacitances at nodes A, B, and C are not equal to the parasitic capacitances at nodes D, E, and F, then small neutralizing capacitors can be added or the turns ratios in the Fig. 3, on page 55, circuit can be adjusted to achieve optimal displacement current cancellation.

If, for example, the total parasitic capacitance of nodes A, B, and C is larger than the total parasitic capacitance of nodes D, E, and F, then we would want to decrease the ac voltage at nodes A, B, and C with respect to the ac voltage at nodes D, E, and F to achieve complete cancellation. This is accomplished by increasing the turns of the windings connected directly to nodes D, E, and F with respect to the turns of the windings connected directly to nodes A, B, and C, so the turns of windings LZ1, LX2, and LY2 are increased, and the turns of windings LZ2, LX1, and LY1 are decreased. Changing the winding turns increases the ac voltage on the windings with increased turns and decreases the ac voltage on the windings with decreased turns; however, the ac voltage per turn remains unchanged, and ripple current cancellation is preserved. Key point No. 3 of Part 1 of this article series asserts this fact and asserts that the windings LZ1, LX2, and LY2 must have equal turns and the windings LZ2, LX1, and LY1 must also have equal turns since all of these windings are coupled on a common core.

The circuit of Fig. 3 can be considered a near-zero emissions power converter. It eliminates two of the largest EMI sources, conducted differential mode emissions at its terminals due to terminal ripple current cancellation and common mode emissions due to balancing and cancellation of the common mode noise sources. By using a multilayer printed wiring board with a solid ground plane and taking care to minimize high dI/dt loop areas, magnetically induced differential mode noise can be significantly reduced. A ground plane reduces common mode noise emissions by creating a mirror image of common mode noise generators, thereby changing monopole sources of common mode noise to dipole sources. Other techniques, such as magnetic shielding, may be needed to eliminate other potential sources of EMI, such as magnetic coupling from external magnetic fields of the inductors.

Circuits with roughly equivalent performance can be realized by adding differential and common mode filters at input and output terminals of a conventional buck converter. In general, eliminating noise at its source, or as close to its source as possible, provides better performance at lower cost and less space than generating the noise and adding filters and shielding to get rid of it. The Fig. 3 circuit adds capacitors, but requires a single magnetic of approximately the same size as the magnetic in a standard buck converter. In comparison to a standard buck converter of the same efficiency, the Fig. 3 circuit will require a slightly larger core window area to accommodate the extra windings. All other known solutions also require adding capacitors, yet can't be accomplished with a single simple core. The amount of terminal ripple current cancellation depends on the amount of capacitance in series with the second windings. The cancellation improves with higher switching frequency and with the amount of uncoupled inductance. It's important to avoid techniques used to minimize leakage inductance. Because the second windings are ac only, it makes sense to wind the magnetic with most of the leakage inductance in the dc windings.

A summary outline of the synthesis method introduced here and in Part 1 of this article series is illustrated in Fig. 5. The outline suggests the synthesis method is applicable to any three terminal network with a winding in series with the Z terminal of the three terminal network. The synthesis method is applicable to any three terminal network of the type indicated and, although Fig. 5 illustrates the synthesis method for a single winding in series with the Z terminal, the method applies to winding networks in series with the Z terminal.

In Part 3 of this series, we'll show how the synthesis method can be applied to other converter types to achieve near zero emissions.

References

1. Carsten, B.W., “Ripple Cancellation Circuit with Fast Load Response for Switch Mode Voltage Regulators with Synchronous Rectification”, U.S. Patent 5,929,692.

2. Wittenbreder, E.H., “Power Electronic Circuits With All Terminal Currents Non-Pulsating”, U.S. Patent 6,304,065.

3. Wittenbreder, E.H., “Power Electronic Circuits with Ripple Current Cancellation”, U.S. Patent 6,437,999.

4. Wittenbreder, E.H., “Synthesis Methods for Enhancing Electromagnetic Compatibility and AC Performance of Power Conversion Circuits”. U.S. Patent Application, serial number 09/946,692.

More on Buck Converters

Buck-Converter Design Demystified
Optimizing Voltage Selection in Buck Converters
Power Conversion Synthesis Part 1: Buck Converter Design
Improving Efficiency in Synchronous Buck Converters > Buck Converter Archive  