Power Electronics

New Technology Enables Paralleled UPS Modules

Inductor dc resistance is utilized in a current sensing scheme.

The focus on the role of power quality in maintaining system availability has been driving innovation in power technology. A new development is Hot Sync®, a patented paralleling technology that eliminates system-level single-point-of-failure. This enables UPS modules to work in parallel with complete synchronization for redundant and capacity systems. The system features two identical modules arranged in a parallel redundant configuration and a parallel tie cabinet connecting the modules to the critical bus. A common bypass input source allows the modules to synchronize their outputs, even when one or both of the parallel system cabinets are open for maintenance. Parallel or capacity systems permit the paralleling of more than two modules, allowing a system load greater than any one module. The Photo shows two-paralleled Powerware 9315 units equipped with Hot Sync.

This technology overcomes a problem faced by power technology engineers: how to parallel UPS modules to provide N+1, N+2, or higher redundancy without introducing a single-point-of-failure. It eliminates the communication wires between the UPS modules, and employs an algorithm that constantly checks each UPS output for any variation. Each UPS operates independently, but in complete synchronization with the other UPS in the system.

The result of this operation is that the UPS modules automatically share the critical load, and they can selectively trip and remove themselves from the critical output bus if an inverter failure or some other critical event occurs. The paralleled outputs, called the critical bus, drive the load.


For two modules in parallel to equally share the critical load, their output waveforms must closely match with respect to frequency and phase angle for all three phases. Unlike traditional, wired paralleling systems, Hot Sync accomplishes this without any communications between the two modules using only the module's output power level. All necessary information for load sharing is available in the module's output power level. Failures in the other module's circuitry, interface circuitry, or system control wiring will not affect the module's output power level.

A Hot Sync system takes advantage of the relationship between the phase angle displacement between two modules and the corresponding power assumed by each module. For instance, if you perfectly match the output waveforms of two modules in parallel, they will equally share the load on the common bus. However, if one module's output phase shifts forward relative to the other module, it will assume more of the common load. This relationship between phase and power is at the heart of Hot Sync load sharing controls.

Load sharing between two modules is very sensitive to the phase angle difference between the two modules. Just a 1° difference in phase angle between two modules results in a 50% load imbalance between them. The load sharing algorithms of a Hot Sync system take advantage of this sensitivity to minimize the phase angle difference between two modules.

Self-Adjusting Modules

In a Hot Sync system, each module monitors its own output 3000 times per second. You can call ΔP the difference in a module's output power between two successive samples. While paralleling, if the first module's ΔP increases its frequency higher than a second module, the first module will proportionally reduce its output frequency. These frequency adjustments are on the order of just a few milliHertz and act as a forcing function for load sharing. In this manner, each module only needs to look at its own output power to remain phase locked with the other module.

This wireless paralleling method doesn't rely on the sharing of information between the two modules and thereby eliminates the need for intermodule communication. In fact, the modules can operate in parallel or alone.

During steady state operation, the modules don't adjust their output frequencies due to the load. The module considers the ΔP value to be zero even with large 100% nonlinear loads. However, during sudden load applications or removals, both modules see the same transient and make a onetime frequency adjustment (backward or forward) to compensate. Again, these output frequency adjustments are on the order of a few milliHertz.

Direct Digital Synthesis

This precise type of paralleling control wouldn't be possible without sophisticated control algorithms in the UPS modules, which are less than two pages of code. To balance the power levels between the two modules, the inverter must constantly make minute frequency changes, as much as 3000 per second in increments as small as 3×10-6 Hz. Such load share control is only possible in modules that employ digital signal processing to control inverter frequency. This technique, using a circular accumulator, updates periodically. The length of the accumulator determines the frequency resolution.

Each module in the Hot Sync system employs a unique load sharing approach. The load share control algorithm maintains synchronization and load share using a stable linear algorithm. The predictability of the algorithm allows a module to simultaneously synchronize its common output to another source, such as bypassing while maintaining load share. The ΔP term maintains load share while the modules in the system are synchronizing to a moving source (such as a generator), and when the modules are synchronizing to different sources.

Selective tripping removes a faulty module from the critical bus before the output is out of specification. This is a two-part process:

  • Identify module outputs that are out of specification limits.
  • Remove the faulty module from the critical bus.

To identify a module failure, the selective trip method looks for changes in module output voltage and current relative to recent output voltage and current. The controls within each module store the output current and voltage waveforms on each of the three phases for the previous cycle. You can compare the moving average of the last five cycles with the present waveforms. From this information, modules can determine if they are the cause for deteriorating conditions. Then, the system removes the faulty module from the line.

A failure that doesn't affect the critical bus is less serious than one that does. For example, if a module failure such as an overtemperature condition due to a clogged air filter occurs, the failure will not impact the critical bus. The other module assumes the balance of the load, and the failed module is isolated from the critical bus. The time required to isolate the failed module from the critical bus isn't significant.

Though most module failures are benign, there are several failure modes that affect the critical bus. Component failure, such as a shorted IGBT, appears as a fault on the critical bus. For these types of failures, it's essential to quickly identify the failure and isolate the failed module for the critical bus. Selective tripping in Hot Sync addresses this issue.

The selective tripping algorithm has been extensively hardware tested. More than 1000 different types of “fault inserted” selective trips were completed during qualification testing. In every case, the selective trip controls successfully identified failure conditions, and just as important, never mistakenly identified normal and faulty conditions.

When a module removes itself from the critical bus, it continues to monitor the critical bus voltage. If the critical bus voltage stays within system specifications, it knows the other module is supporting the critical bus. However, if the critical bus voltage drops when the faulty module isolates itself, it knows the other module is off-line and the critical bus needs support. The faulty module will then close its bypass path, and the resulting bus interruption will not exceed 0.004 sec.

How It Works

Hot Sync's load sharing technique employs a current transformer connected to the input terminal of the IGBT inverter (Fig. 1). This enables detection of the dc input current flowing into the IGBT inverter. The detected dc input current and voltage signals are then sent to respective A/D converter channels of a 16-bit high-speed microcontroller where they are sampled. The micrcontroller output controls the 3-phase output frequency of the IGBT inverter, which enables the paralleled power system to share the load equally. The sample rate for this power information should be above 2 kHz and can use the ac output of the UPS inverter instead of the dc input for sampling power. In addition, the microcontroller also provides a trip signal to remove the power system from the power supply circuit if a fault occurs.

The microcontroller controls load sharing in response to processing of the sampled dc input current and voltage signals (Fig. 2). In the preferred configuration, the microcontroller processes the received dc current and voltage samples. It then provides the resulting gate drive signal to the IGBT inverter in a manner that forces it to load share with the other parallel power systems. Alternatively, you can sample the power level directly using a power transducer and then provide it to the microcontroller. Preferably, this is implemented in the firmware of the microcontroller, although it can be implemented in software or special purpose hardware as desired.

In the first step of the flowchart load sharing process (Fig. 2), the microcontroller receives digitized dc voltage and dc current samples. Next, it multiplies them together in Step 2 to compute the dc input power to the IGBT inverter. Thus:

pn=Vn×In (1)

Pn=K2×pn (2)


Vn=Digitized dc voltage samples received by the microcontroller

In=Digitized dc current samples received by the microcontroller

pn=dc input power to the IGBT inverter

Pn=Output power of IGBT inverter

K2=Constant gain that defines the dynamic response of the inverter.

Step 3 computes:

Δpn=pn-pn-1 (3)


Δpn=change in input power

pn-1=Input power of the previous dc input samples

In Step 4, the change in input power is integrated over the inverter's input frequency range to yield:

fn=fn-1- (K1×Δpn)-(K2×pn)


Δpn=Change in input power

fn=Inverter frequency

fn-1=Inverter frequency for the previous dc input samples

K1 and K2=Constants that define the dynamic response of the power system

The microcontroller then outputs an IGBT gate drive signal to IGBT inverter in Step 5 to drive output power to the frequency, fn. Then, the load share routine exits in Step 6.

We use the rate of change for the output power to force the frequencies of the respective inverters together to a fixed frequency or a frequency of an alternate power source for the respective power systems. The power levels of the power systems will change due to differing power system frequencies. The power level itself biases the inverter output frequency to correct for steady state load errors for load sharing. The system doesn't need a digital synchronizing signal or difference from average analog signal to change an inverter's output frequency.

Hot Sync controls the IGBT inverter's output frequency to either run at a fixed frequency or to synchronize to an alternate power source. In the ideal configuration, the frequency updates at a 3 kHz rate due to the input power level of the IGBT inverter. The frequency also updates once per ac output voltage cycle to either run at a fixed frequency or to synchronize (e.g. phase lock) to an alternate voltage source.

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