Power Electronics

New Power MOSFET Packages Cut DC-DC Converter Size

Smaller packages exhibit better thermal properties than older versions.

With the majority of dc-dc converters now using surface mount technology, there's a need for low-profile, surface-mountable power MOSFETs with the necessary dissipation and thermal properties. The popular D2PAK and DPAK provide the appropriate power dissipation, but their physical size limits converter packaging density. Some converters employ the smaller SO-8 power semiconductors, but they have limited power dissipation capability. Therefore, the dc-dc converter community needs smaller power semiconductor packages with the power dissipation attributes of their larger counterparts.

Besides physical size, power semiconductors for dc-dc converters require high cell density silicon to reduce RDS(on), and therefore conduction losses. You can achieve this by employing the trench process, which has advantages over the traditional planar process at cell densities above 12 million cells. Along with other parameter improvements, current power MOSFETs can now operate efficiently at frequencies in excess of 300 kHz.


PowerConnect technology responds to the need for smaller, efficient, power semiconductors with the appropriate power dissipation capability. It's a natural extension of the standard SO-8 package with the source bond wires replaced by a copper lead frame. The package looks the same from the outside, but 3mΩ reduce package resistance. Reducing the package interconnect resistance to less than 1mΩ is significant when the silicon provides an RDS(on) of less than 10mΩ.

Fig. 1, on page 26, shows the cross section of a bond-wired SO-8 package. Fig. 2, on page 26, shows the cross section of the PowerConnect or bond-wireless SO-8 package. Table 1 compares PowerConnect SO-8 devices with standard SO-8 devices. The Si4838DY, with an RDS(on) of 3mΩ, achieves the lowest value in the SO-8 package.


The newest family of power packages is the PowerPAK, shown in the Photo, above. This packaging technology enables devices with thermal resistance <1°C/W, or about the same as a twice-as-large, twice-as-thick DPAK power MOSFET. In contrast, thermal resistance is 16°C/W for a single-channel, standard SO-8.

PowerPAK devices achieve this improved thermal performance by providing a direct thermal path from the backside of the copper die attach pad to the p. c. board. The main thermal path is through a large copper pad exposed on the bottom of the package, which improves thermal resistance dramatically. Package thickness is also reduced, enabling a higher density dc-dc converter layout. In contrast, the conventional SO-8's main thermal path is through its leads, which is not as efficient.

Besides the enhanced thermal performance, PowerPAK on-resistance is low for its package size — comparable to best-in-class DPAK power MOSFETs. The new SO-8 PowerPAK offers the same cavity size, so it can use the same die as devices housed in the DPAK package.

The PowerPAK SO-8 has the same footprint and pinout as standard SO-8. The PowerPAK 1212 uses the same footprint but has a smaller footprint of 3mm2. Unlike power MOSFET packages with an exposed die, PowerPAK's design provides a consistent footprint regardless of the particular silicon used in a given device, eliminating the need for retooling to accommodate devices with different on-resistance ratings.

PowerPAK also addresses the power demand challenges of the next generation of microprocessors by handling higher current densities without increasing the board space occupied by power semiconductors. It does so without generating additional heat.

Table 2 compares the steady state values of Rθjc and Rθja for DPAK, SO-8, PowerConnect SO-8, PPAK SO-8, PPAK1212, and TSSOP8. This displays the advances made in the reduction of thermal resistance with new package introductions.

To demonstrate the thermal impact of PowerPAK, you can consider the example of a DPAK, PowerPAK SO-8, and a standard SO-8 using the same die, as shown in Fig. 3. Each package mounts on a p. c. board where the Rθca is 30°C/W, Ta is 25°C, and the power dissipation is 2.7W. Evaluating the junction temperature for each package:

Tj=Junction temperature
Ta=Ambient temperature
PD=Power Dissipation
jc=Junction-to-case thermal resistance
ca=Case-to-ambient thermal resistance
Resulting junction temperatures are:
PowerPak SO-8=107.7°C

Besides providing thermal headroom, lower junction temperatures can reduce conduction losses. Remember that the RDS(on) of a MOSFET increases as the junction temperature increases. With the junction temperature at 150°C, the RDS(on) can be almost twice the value at 25°C.

When comparing a PowerPAK SO-8 to a standard SO-8, the junction temperature of the PowerPAK would be 25°C cooler than the SO-8 when dissipating 1.8W. The slope of the curve in Fig. 4, on page 28, shows that this reduction in junction temperature represents a reduction in RDS(on) of about 15%. Considering that conduction losses are defined by PD=I2×RDS(on), they are reduced by 15%. In some dc-dc converters, where every bit of efficiency is valuable, this is a simple way to significantly reduce losses.

Silicon Advancements

Increasing cell densities enable power MOSFET manufacturers to reduce RDS(on) for a given die size. Qg (gate charge) decreases for a given RDS(on). As a result, dc-dc converters benefit in a number of areas. One example is a reduction in conduction losses and switching losses. You can also use smaller MOSFET packages, allowing higher density packaging of the converters — a continuous trend.

As converter technology moves forward, consumers place new demands on the power MOSFETs. The traditional figure of merit, Qg×RDS(on), is no longer sufficient to insure improved efficiency. You must pay close attention to the values of Qgs (gate-source charge), Qgd (gate-drain charge), and Rg (internal gate impedance).

The core voltage converter in a notebook computer is a good example of having to pay attention to multiple parameters. This synchronous converter must drop battery voltages as high as 20V down to 1.6V. The low, required-duty cycle puts different parametric constraints on the control and synchronous MOSFETs. The control or top MOSFET spends more time switching than in conduction. Qgs, Qgd, and Rg affect the switching speed and carry more weight than RDS(on). Minimize Rg to take advantage of the reduced gate charge. Use wide gate bus techniques to reduce this figure. Consider target values as low as 1Ω as a typical in datasheets.

The synchronous or bottom MOSFET spends most of its time in conduction, making RDS(on) appear to be the most important parameter. The exception is the drain of the synchronous MOSFET exposed to high dV/dt when the MOSFET is off. You can couple this dV/dt back to the gate by the Miller capacitance (Cgd) turning the synchronous MOSFET on, causing shoot-through current. You can prevent this effect by controlling the ratio of Qgs to Qgd. A ratio of two is considered desirable.

Cell Density

The never-ending push to higher cell densities obtained 178M cells/in.2 with the promise of going beyond. Fig. 5 displays the improvement in RDS(on) achieved with the increase in cell density in various steps up to a 178M cell. From the normalized figure of 32M cells, you see a 35% improvement with a 10V, VGS drive. With a 4.5V, VGS drive, the improvement in RDS(on) is impressive, with a 45% reduction. This characteristic meets the trend by the controller manufacturers in providing a 5V gate drive. These devices should improve switching and conduction losses to meet the demands on power MOSFET specifications.

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