Decoupling and bulk capacitance are used to limit the voltage deviation of dc-dc converters in the face of load steps. Yet, requirements for high power density and low cost often dictate that the amount of external capacitance be minimized. One way to do this is by modeling the response of the dc-dc converter to estimate its overshoot/undershoot and settling time in response to predicted load steps. In “Predicting Load Transient Response of Output Voltage in DC-DC Converters,” presented at this year's Applied Power Electronics Conference, Cahit Gezgin of Tyco Electronics Power Systems describes how a converter's transient response may be modeled using a second-order RLC circuit with values from measured voltage loop data (**Fig. 1**).

For a given load step, the voltage deviation predicted by the model closely approximates actual measured values. This technique also shows that transient response requirements can be met with lower values of capacitance than predicted by calculations of a converter's target impedance. That parameter (Z_{target}) is defined as the peak magnitude of the dc-dc converter's closed-loop output impedance in parallel with the total impedance of the capacitors positioned at the load plus PC board trace impedance.

To create the model, the values of the RLC components are chosen so the converter in question and the RLC circuit exhibit the same voltage undershoot and settling time in the face of a 5-A load step. The circuit is then used to obtain a first-order approximation of the converter's ΔV and settling time under a load transient.

The author first determines the dynamic response of the RLC circuit to a load step, deriving the following equations for voltage deviation (ΔV) and settling time (T):

where Q_{0} = R(C/L)^{1/2}. Settling time is expressed as

where Q_{0} > 1 (underdamped) or

where Q_{0} < 1 (overdamped) and ω_{o} is the resonant frequency and a is the damping ratio (α= ω_{o}/2Q_{o}).

The author then creates the macro model of the dc-dc converter shown in **Fig. 2**, which is related to the RLC circuit in terms of Q_{o}:

(where Ф_{m} is the phase margin of the voltage loop) and R, which may be expressed as the parallel combination of the closed-loop output impedance (Z_{OL} /(1+AB)) and load impedance Z_{L} at the voltage loop crossover frequency. In addition, I_{L} is the step change in load current, while ω_{o} is the crossover frequency of voltage loop gain (γ_{o}·A·B), also known as the control loop bandwidth. Once Q_{o} and R are calculated, the ΔV of the RLC model can be calculated as above. Similarly, settling time may be calculated as a function of Q_{o} and ω_{o}.

To determine Q_{o} and R, you must obtain values of phase margin, crossover frequency and closed-loop output impedance for the dc-dc converter. Obtain these parameters by using the Stability Analysis Tool described in the paper referenced by Gezgin. This tool calculates Bode plots of the converter's voltage loop under varying output loads and remote voltage sense locations.

With this approach, the results obtained for ΔV reflect performance at the sense location rather than the load. Also, an infinite current slew rate is assumed. However, this approach will accurately determine ΔV for current slew rates greater than 1 A/µs, when used to test the performance of isolated dc-dc converters with crossover frequencies below 10 kHz. For more information, contact the author at [email protected]

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