Most microstepping motor drivers require control lines for DACs to set the reference for the PWM current regulator and phase inputs for current polarity control. In more sophisticated drivers, inputs are required for the PWM current control mode to operate in slow, fast, or mixed decay. These control lines can quickly add up to 8 to 12 inputs, depending on the DAC resolution and the necessity of a supply from a system microprocessor. The requirement of these control inputs and complex sequencing tables in the microprocessor add to the system's cost and complexity. A new microstepping motor driver IC, the A3977, solves this problem with its simple 2-line Step and Direction interface and an efficient DMOS output (see Fig. 1). For each transition in the Step input, the driver sequences one microstep. This is ideal for unavailable or overburdened microprocessor-controller applications.
A stepper motor system will have reduced audible noise if the microstepping driver can switch between slow and mixed decay mode PWM operation. This device includes circuitry that automatically sets the current-decay mode to slow or mixed decay, eliminating the need for the user to provide additional control lines.
To satisfy high-end applications that require low power dissipation, the A3977 uses low RDS(ON) N-channel power DMOS outputs rated at ±2.5A and 35V. Also, the IC's synchronous rectification control circuitry turns ON the appropriate output DMOS device during the current decay, effectively shorting out the body diodes with the low RDS(ON) driver. This results in lower power dissipation and eliminates the need for external Schottky diodes in most applications. This next generation microstepping motor-driver IC combines low power dissipation and high current outputs, efficient current control, and a simple-to-use interface.
PWM Current Control
A fixed off-time PWM current control circuit controls each DMOS H-bridge, limiting the load current to a desired value (Itrip). Initially, the circuit enables a diagonal pair of source and sink DMOS outputs and current flows through the motor winding and the current sense resistor (RS), as shown in Fig. 2. When the voltage across RS reaches the DAC output voltage, the current sense comparator resets the PWM latch, which turns off either the source drivers (slow decay mode) or both the source and sink drivers (fast or mixed decay modes) and the current recirculates. During this recirculation, the current decreases until the fixed off time expires. The circuit enables the appropriate output drivers again, the motor winding current again increases, and the PWM cycle repeats.
The selection of RS and the voltage at the VREF input sets the maximum value of current limiting. Its approximate transconductance function is Itrip(MAX)=VREF/(8×RS) (1)
The DAC output reduces the VREF output to the current sense comparator in precise steps (See Table 1, on page 53, for % ItripMAX at each step). Itrip=(% Itrip(MAX)/100)×Itrip(MAX) (2)
The internal PWM current control circuitry uses a one-shot to control the time the driver is off. An external resistor (RT) and capacitor (CT) connected from the RC timing terminals to ground determine the one-shot off-time (tOFF). The approximate tOFF is tOFF=RTCT (3)
Besides the fixed off time, the CT component sets the comparator blanking time. This feature prevents false overcurrent detection due to reverse recovery currents of the clamp diodes, and/or switching transients related to the capacitance of the load and eliminates the low-pass filter between RS and the current-sense comparator required on most PWM current regulators. Approximate blank time is tBLANK=1900 CT (4)
Each of the two H-bridge outputs provide full-, half-, quarter-, and eight-step microstepping operation for a bipolar stepper motor. The A3977 translator converts its Step and Direction inputs into the control signals required to sequence the current in the H-bridge for the appropriate microstepping.
At power up or reset, the translator sets the DACs and phase current polarity to the initial Home state conditions and sets the current regulator for both phases to mixed decay mode (see Figs. 3 through 6, on pages 51 and 52). When a step command signal (logic high-to-low transition of the Step input) occurs, the translator sequences the DACs to the next level and current polarity. Table 1, on page 53, shows the current sequence for clockwise motor operation (Direction input logic low). For counterclockwise operation, the Direction input is set to logic high and the translator reverses the sequence. The PWM current regulator uses the DAC outputs to set the trip point of the current output of each phase. Inputs MS1 and MS2 set the microstep resolution, as shown in Table 2, on page 53.
Mixed Decay Operation
The automatic mixed decay feature of the A3977 optimizes the current-chopping mode for the best sinusoidal current waveform for microstepping.
Slow decay (Fig. 7) has the advantage of minimum current ripple. However, when microstepping at higher step rates, slow decay chopping may fail to properly regulate current on the backside of the sine wave when current drops — a result of motor BEMF overriding the voltage applied to the motor, forcing the current to increase during the decay. Fig. 8 is a scope plot of A3977 motor current that illustrates the limitations of slow decay chopping. This distortion in the current causes increased audible noise in the motor.
Fast decay (Fig. 7) solves the current regulation problem of slow decay. With approximately the full (-) supply across the motor winding, it can quickly get the current out of the winding. The disadvantage of fast decay is the increased current ripple, which in turn causes increased motor heating.
Mixed decay (Fig. 7, on page 52) splits the fixed off time of the PWM cycle into fast and then slow decay. When the current reaches Itrip, the device goes into fast decay mode until the voltage on the RC pin decays to the voltage on the PFD pin (VPFD). The approximate time the device operates in fast decay (tFD) is tFD=R×C×ln(VDD×0.6/VPFD) (6)
After this tFD portion, the device switches to slow decay mode for the remainder of the fixed off time period. The result is low current ripple, but with increased bandwidth to track the ideal sine wave for microstepping.
Although mixed decay improves microstepping performance, it still has higher current ripple than slow decay. The best solution is to use a slow decay on the front side of the sine wave and mixed decay on the backside of the sine wave output. When a step command signal occurs on the Step input the translator sequences the DACs to the next level. If the new DAC output level is lower than the previous level then decay mode for that H-bridge will be set by the voltage level on the PFD input (fast, slow, or mixed decay). If the new DAC level is higher or equal to the previous level, then the decay mode for that H-bridge will be slow decay. Fig. 9, on page 54, is a scope plot of the A3977 with slow decay on the front side and mixed decay on the backside. For comparison, see the motor current scope plot of the A3977, set to 100% fast decay on the backside of the sine wave and slow decay on the front side in Fig.10, on page 54.
After triggering a PWM off cycle, a bridge disable command or internal fixed-off time cycle, load current will recirculate according to the decay mode selected by the control logic (Fig. 2, on page 51). The A3977 synchronous rectification (SR) feature will turn on the appropriate DMOS drivers during the current decay and effectively short out the body diodes with the low RDS(ON) driver (Fig. 11, on page 54). In fast decay synchronous rectification mode, the circuit monitors the voltage across RS to prevent reverse conduction. Just before the recirculation current reaches zero, the circuit turns off all of the DMOS drivers and current flows through the body diodes.
In a typical stepper motor application, the motor driver IC is in current-decay (recirculation) mode for a higher percentage of the PWM cycle than on time. Thus, most of the power dissipation is a result of the forward voltage drop of the internal body diode of the power DMOS. This is apparent in the first-order power calculation of output power dissipation (Pd) in slow decay recirculation mode — with and without synchronous rectification enabled. Assume:
RDS(ON)=On resistance of the sink
VFD=forward voltage drop of the sink
DMOS body diodes=1.4V
Synchronous rectification enabled:
Synchronous rectification disabled:
Power dissipation savings by using the A3977's synchronous rectification feature can eliminate the need for external Schottky diodes in most stepper motor applications, saving the cost and board space for these components.
The A3977 uses the Sleep input to minimize power consumption when not in use. This disables much of the internal circuitry, including the output DMOS, regulator, and charge pump. Total logic plus motor supply current in sleep mode is <40μA. Logic low will put the device into sleep mode; logic high allows normal operation and starts up the device in home position. The A3977 sleep mode feature is critical in new designs requiring low off-state current.
The Enable and Reset inputs turn on or off the DMOS outputs. Translator inputs are independent of the Enable input state so the outputs can be disabled and stepped to a defined microstep state and then re-enabled in this position. The Reset input resets the translator to the home state.
The Home output is a logic output indicator of the initial state of the translator. At power up, the translator is reset to the Home state. The Home output current level is common to all four microstepping levels in the A3977. You can use this current as a control input, indicating the microstepping resolution can be changed at this step without causing current and torque disturbance to the motor.
An undervoltage lockout circuit protects the A3977 from potential shoot-through currents with the motor supply voltage applied before the logic supply voltage. All outputs are disabled until the logic supply voltage is above 2.7V; the control logic can then correctly control the state of the outputs. Thermal protection circuitry turns off all the power outputs if the junction temperature exceeds 165°C. This protects the A3977 from failure due to excessive junction temperature and will not necessarily protect it from output short circuits. Normal operation resumes when the junction temperature decreases about 15°C.
The A3977 is available in two power packages, a 44-pin plastic power PLCC package and a 28-lead eTSSOP package. The 44-pin PLCC has four copper “batwing” tabs for maximum heat transfer and a thermal resistance of 32°C/W. The 28-lead eTSSOP measures 9.7 mm×4.4 mm×0.9 mm and has a thermal resistance of 38°C/W. It's less than one-fourth the size of the PLCC package and achieves nearly the same thermal resistance. The smaller size IC is an important advantage in applications that have extreme space considerations.
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