Today's microprocessors have a voracious appetite for power. Within a fraction of a microsecond, their current consumption can soar to 60A. As their power dissipation increases with the number of transistors and the supply voltage drops, the core current (ICC) continues to rise with each new generation as the quotient of power divided by voltage. This has resulted in tougher specifications for the switching controllers or dc-dc converters that supply the voltage for the microprocessor and also calls for sustained optimization of passive components. The emergence of new capacitor technologies featuring extremely low ESR and equivalent series inductance (ESL) in conjunction with high capacitance has made efficient, space-saving and low-cost designs possible.
The voltage supply to the processors has to cope with extreme load changes — such as shifting from operating mode to sleep mode and back again, as the core current jumps from 0A to a peak of 60A, depending on processor type. The rising edges of these current surges are steeper than 450A/µs in today's processors.
Fig. 1 shows a typical load change. Here, ICC jumps from 0 to a maximum ICC(max) after a delay ΔtµP. Typical values for ΔtµP are 0.1 to 0.2 µs. The supply voltage needs a period of time ΔtPS to stabilize itself at its maximum value. In the period elapsing between 0 and ΔtPS, the voltage must be buffered by capacitors. A two-stage capacitor concept allows this function to be performed optimally.
First, several multilayer ceramic capacitors (MLCCs) of low capacitance and ultralow ESR are mounted right in the socket and beneath the CPU on the power plane as a coupling capacitance CF. The good electrical connection allows them to discharge extremely quickly, and they can be placed close to the core thanks to their compact size (0603, 0402).
Second, several capacitors of higher capacitance and ESR are then placed around the processor as a bulk capacitance CB. This configuration ensures that the capacitance CF is discharged in the first few microseconds after the change of load and thus supplies the output required by the processor. The bulk capacitance CB then begins to release its charge as the current ICB. The critical point is to scale the bulk capacitors so they don't take up too much space on the board, but can simultaneously discharge quickly and long enough to bridge the gap between the time that CF has spent its charge and the converter begins to supply its current IPS.
Fig. 1 shows the dip in the core supply voltage during ΔTP caused by the voltage drop across ESR and ESL. After ICC reaches a steady value, the core voltage VCC rises briefly and then keeps dropping as CB discharges. Voltage regulation then returns the core voltage to its maximum value VCC(max). The maximum current the power supply with the two capacitances can provide must be substantially higher than ICC(max) that can be reached during load changes. Otherwise the processor triggers an interrupt. The actual core current is limited to ICC by the processor.
The core supply voltage VCC must satisfy similar requirements. The semiconductor manufacturer specifies a voltage tolerance, ΔVCC, that represents the maximum fluctuation width of VCC around the reference voltage VCCRef [VCC(max) - VCC(min)]. If the voltage leaves its defined window, an interrupt is also triggered. The voltage tolerance is typically 2% for the Intel Xeon processor and 4.5% for the AMD K6-III. On the basis of these values, we can summarize voltage supply requirements as:
- High efficiency, i.e. low-power dissipation even for load currents exceeding 50A
- Short response times
- Minimal need for external components
- Low space requirement
Fig. 2 is the equivalent circuit of a section of the motherboard design with the dc-dc converter, the two capacitances CB and CF, and the processor input. The output of the switching controller is depicted as VIN, and the bulk capacitor with its ESR, ESL, and its ideal loss-free capacitance CB. The coupling capacitor CF and the inductive and resistive losses of the interconnections with the processor (p. c. board trace) and under it (power plane) are included for the sake of completeness. The interconnection losses are compensated by CF.
When considering the bulk capacitance, you can neglect the load's input resistance, RL, and input capacitance, CL, (in this case the processor). The following special requirements apply to CB:
- Power supply to the core within the switching controller delay ΔtPS
- Compensation of low-frequency interference
- When loads change, any dips of VCC below the specification limit must be prevented
You can use the following relationship to determine the total required capacitance Ctot:
ΔI = Surge current
ΔV = Voltage change at the capacitor during an interval Δt for a given ESL and ESR
Assuming VCC must not leave the defined voltage window between VCC(min) and VCC(max) as an interrupt is otherwise triggered, calculate the maximum permissible value for ESRtot:
The current flowing from the capacitor is:
Tantalum chip capacitors, especially those made with an innovative polymer single and multianode technology, are suitable as bulk capacitors. The table lists tantalum capacitors currently available in various technologies. MnO2 types are suitable as low-ESR capacitors rated up to 50V. In all polymer-based capacitors, rated voltage is currently limited to equal or less than 10V. Single-anode polymer solutions can thus satisfy the requirements for high capacitance and ESR below 40mΩ. Polymer multianode types go one step farther with ESR below 10mΩ for the second stage. Thermal change in the polymer at high temperatures currently limits the operating temperature ceiling to 105°C.
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