Power consumption of modern microprocessors has been increasing as clock frequency and the number of transistors have grown. The general trend has increased maximum processor power consumption by a factor of a little more than two times every four years. Advanced power management can also drop the PC to a low power level when not in use and quickly resurrect the computer on demand, which can cause a large, almost instantaneous current surge.
While power demands increase, the core voltage of the latest microprocessors has significantly dropped. To avoid voltage drops that may cause the microprocessor to fail, designers have to wrestle stray inductance and resistance — including circuit traces and connector resistance. Operation at low voltages, GHz clock rates, high power, and the ability to survive fast current transients requires a new generation of voltage regulator modules (VRMs).
VRMs are high-speed (>200 KHz switching) dc-dc converters providing a distributed power supply architecture that reduces the current path and allows fast transient response. Although a great benefit in the application, it challenges manufacturers to develop an effective method of testing these VRMs on the production floor. Traditional test equipment and fixtures have proven too slow to simulate transients that are hundreds of amps per microsecond.
To ensure proper VRM operation, the VRM must operate within specifications after it has been installed on the motherboard, the test must effectively simulate a full scale or partial load step, and testing must effectively perform load steps at very low operating voltages.
Like traditional dc-dc converters, VRMs require tests against ripple, noise, efficiency, line and load regulation, and even current sharing. In addition, a unique VID (voltage identification) control, which allows the processor to control the nominal output voltage, requires testing.
Proper care is essential for the voltage measurement point, defined to be at the processor terminals. You may also add additional resistors, capacitors, or inductors on the test fixture to simulate circuit impedance. For example, Intel VRM 8.4 design guidelines define a minimum 1.5Ω, 1nH resistor and inductor to simulate the p. c. board layout impedance from Vcc to Vss.
Transient response is the most important VRM test and the most difficult to perform. A VRM must maintain regulation under high transition rate loading, so it's crucial to generate a fast load pulse or single transition to verify the voltage transient levels and transient response time under specified loading. As with traditional power supplies, different loading patterns can cause significant differences in transient response time and voltage level. Therefore, an electronic load that simulates fast load changes is necessary to verify a VRM's transient response.
When evaluating different VRM test platforms, it's best to return to the fundamentals of any power supply testing. First, you should be able to measure the test; second, you should be able to repeat it with no change in the results when tested under the same conditions. Third, you must be able to verify the accuracy of the test condition simulators while making sure the measurement devices are verifiable and easily calibrated.
Fig. 1 shows a typical design for an electronic load to test VRMs. It's important to give this design proper attention to achieve the high slew rates required for proper VRM testing. These limitations come from several different circuits and components.
- The response speed (Tr) of the control loop.
- The total resistance of the shunt, connector and RDS(ON) of the MOSFET (R).
- The total inductance of the connection and internal inductance of MOSFET (L).
- Turn on and turn off time of the MOSFET (Tf).
- The maximum transient loading level of the step loading (I).
First, Tr and Tf, whichever is greater, will define the rise time to an electronic load (E-load), regardless of the load setting. For instance, if the higher value of Tr and Tf is 1μsec, then the maximum allowed slew rate under 100A and 10A step loads is limited to 100A/μsec and 10A/μsec, respectively.
A second consideration is the bias voltage or the fundamental operation level for an electronic load to draw current from the VRM PSU (Power Supply Unit). Other factors influence this minimum operation voltage (Vmin) for the E-load; you can express them as:
Vmin = (I×R) + (L×SR) + Vx(1)
Where: SR = Slew rate
Vx = Constant.
Fig. 2, on page 55, illustrates the dynamic relationship of loading levels and slew rate. When you can't ignore the R and L and you've set the minimum operation voltage of the E-load to a certain level, the relationship between the loading level and the maximum allowed slew rate will be the solid line. From the solid line, when the loading level (I) is very high, the corresponding drop in the operation voltage (Vmin) will be too low to support the voltage drop caused by a high slew rate (L×SR). The circuit resistance is a dominant factor in the slew rate.
When the loading level decreases, you can push the slew rate (SR) higher due to lower voltage drop caused by circuit resistance (I×R). In this case, the dominant factor in the maximum allowable slew rate is the control loop bandwidth (Tr) and MOSFET turn on/off time (Tf). The slew rate decreases in proportion to the loading level.
Thus, the first challenge to push the slew rate higher is to increase control loop feedback bandwidth and select a shorter Ton/Toff MOSFET without sacrificing the power rating (Fig. 2).
Fig. 3 shows how under the same input voltage (Vmin), lower circuit resistance pushes the slew rate and loading level higher. When the circuit inductance is lower you can push the slew rate higher — also under the same Vmin, as shown in Fig. 4. Finally, as you can see in Fig. 5, Vmin directly affects the slew rate and maximum allowable loading level.
Design challenges for a high-slew rate (HSR) electronic load include lowering the control loop response time, MOSFET turn on/turn off time, circuit resistance, and inductance. Do this while the input voltage is low and load current is simultaneously high.
In testing VRMs, most engineers have had to rely on Equation (1) to develop custom loads. Until recently, no commercial off-the-shelf loads were available that had the necessary slew rates and fixtures to test VRMs. The first commercial high slew rate load is the 6340 series. Two models are currently available; one can program slew rates up to 100A/μsec at 1 μsec minimum rise time and the other up to 150A/μsec at 500 ns minimum rise time. Figs. 6 and 7 show the relationship of these two HSR loads under 0.8V (Fig. 6) and 0.5V (Fig. 7) operation.
The test fixture will also significantly influence slew rate performance. Fig. 8, on page 57, shows a typical test setup using the 6340 series load. The test fixture is designed in accordance to VRM8.4, and the voltage is measured at the end of the soldering point of the fixture p. c. board. The maximum slew rate was determined by checking the rise/fall time (5% to 95%/95% to 5%) and confirming no current waveform distortion.
On-board VRM testing
All VRMs will eventually mount on the p. c. boards next to the microprocessors. The board layout and soldering quality will directly affect the voltage waveform and levels the microprocessors receive from the VRMs. Therefore, it will be necessary to measure the transient voltage level at the microprocessor socket under transient step loading to see the actual voltage waveform fed to the microprocessors.
Based on this concern, Intel had released a series of transient load testers called VTT (voltage transient tester). This standard will require specific fixtures to test at each processor socket. It will also require different load stages for each processor standard, such as socket 370, 423, etc.
Fig. 9, on page 55, shows a possible test set up to meet the VTT standard. This unique design can be used as an R/D verification and manufacturing batch testing tool for both VRM and PC motherboard manufacturers. However, further evaluation will be needed before production line testing can be implemented.
Future VRMs and HSR Loads
With the increasing clock speed of microprocessors, a frequently asked question is: Can HSR loads or VRMs keep up with the speed of future microprocessors? As the speed of the microprocessor reaches beyond 10 GHz or even 100 GHz, a separate VRM won't be able to supply sufficient instantaneous current because the inductance of the trace on the p. c. board will cause unacceptable voltage drops.
Meanwhile, the core voltage of the new microprocessor can only go lower. Any drop on the lead will cause the microprocessor to fail. Therefore, the ultimate solution is to use semiconductor technology to integrate an embedded dc-dc converter onto the microprocessor. But, this will require a revolutionary breakthrough in semiconductor technology that will not be available in the foreseeable future.
Basic physics and material properties are still the prominent factors in developing a viable HSR load. Engineers must pay attention to the design details of the actual load, and the VRM test fixture and interconnects.
Following the fundamental rule of testing points away from a hot-mockup processor board for a test tool to an E-load based test bed. These HSR loads may not be as fast as the transient loading drawn by the processor, but they offer correlated test data. Using an HSR load is the best solution to test transient characteristics of VRM high-speed dc-dc converters.
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