Power Electronics
DSP Controls 48V Supply with Battery Backup and PFC

DSP Controls 48V Supply with Battery Backup and PFC

Active current shaping using flyback ac-to-dc converter provides power factor control and dc voltage regulation.

Distributed power supplies will be the new architecture for next generation PCs and servers superscript [1]-[2]. Fig. 1 shows the general architecture for a distributed power supply system for these high-performance desktop units. The backbone in such a system is a 48Vdc power bus. The front-end power supplies provide the interface between the utility and 48Vdc power bus, while the dc-dc converters provide voltage regulation for the high-demanding load. Design requirements for the front-end power supplies are high efficiency, low harmonics distortion, fairly good voltage regulation, current sharing control, power management control with optional power diagnosis, and battery backup.

Digital signal processor (DSP) digital control techniques provide the appropriate design and implementation of this 48Vdc power supply with power factor (PF) correction and battery backup, for use in a distributed power supply system with 48Vdc power bus. The output voltage of this system can be backup and voltage compensated by a battery-connected dc-dc converter under DSP-based digital control. A bilateral control mechanism for the charge and discharge of the battery operates as an interactive uninterruptible power supply (UPS) with 48V output dc voltage. DSP-based software control techniques for the UPS have been developed for the control and power conversion of the ac-dc and dc-dc converters.

Fig. 2 shows the proposed control architecture for the battery-backup 48V power supply. A single-chip DSP controller, the TMS320F240, is used for the realization of the control algorithms for the control of this front-end power supply. A boost-flyback converter with active input current shaping technique is used for PF control and dc voltage fast regulation superscript [3]-[5].

Circuit Description Fig. 2 shows the proposed dc UPS, consisting of a flyback ac-dc converter and a bidirectional dc-dc converter. Input line current shaping for PF correction is included in the flyback ac-dc converter that provides an isolated 48V output. The bidirectional dc-dc converter consists of a pair of back-to-back buck and boost converters with three operating modes: normal, charging, and backup mode.

The dc UPS operates in normal and charging mode when the main utility line is properly functioning, providing a high PF with fast response regulation of the output dc voltage. If there is an eventual failure of the utility, the dc UPS will switch to its backup mode and maintain the output voltage with fast dynamic response. Usually, the normal mode is controlled by switch Q subscript 1 by means of PWM1, the battery charger is controlled by switch Q subscript 2 by means of PWM2, whereas the backup mode is controlled through the switch Q subscript 3 by means of PWM3. The states of the switches Q subscript 1, Q subscript 2, Q subscript 3 for each operation mode are summarized in Table 1, on page 63. Fig. 3, on page 60, shows the equivalent circuits of normal (a), charging (b), and backup (c) modes.

Normal Mode When the utility is normal, the dc UPS operates in normal mode and the flyback ac-dc converter operates in discontinuous conduction mode (DCM) with regenerative clamping superscript [3]. This converter is a combination of a boost PFC and a flyback dc-dc converter by sharing the same power switch, Q subscript 1. You can find a detailed description and characteristic analysis of this flyback ac-to-dc converter in superscript [3].

Fig. 4, on page 63, shows the block diagram of the digital PFC controller for the flyback ac-dc converter. The digital PFC controller was realized by using a single-chip DSP controller, the TMS320F240. The instantaneous values of the rectified line voltage, input inductor current, output voltage, and the load current are fed back for synthesis of the PWM signal.

The PWM switching frequency is set at 80 kHz. The sampling frequency for the voltage loop controller is set at 5 kHz and 20 kHz for the current loop. Therefore, the output duty ratios of the PWM generator was updated every 100 sec. The internal event manager module of the DSP controls the generation of the PWM signals.

When the load is nonresistive, the sense of the load current provides extra load information. The voltage loop controller is a PI controller with weighted load current feedback. Voltage loop controller output is the averaged current command for the inner current loop that corresponds to the required average value of input line current.

To generate a synchronized current reference command, the voltage loop controller output is then multiplied by the rectified line voltage. This half-wave sinusoidal current command is then applied to the inner current loop controller. Comparing this with the outer voltage loop, a higher bandwidth is required for the inner current loop.

In the design of a PFC controller, the bandwidth of the voltage loop should be kept lower than twice of the line frequency to provide a compromise between power quality and output dc voltage regulation.

Charging Mode In the charging mode, the bidirectional dc-dc converter is connected to the secondary side of transformer. As shown in the equivalent circuit in Fig. 3(b), Q subscript 2, D subscript 3 and L subscript u constitute a buck converter. When operating in the charging mode, power flows from the dc-link to the battery. One advantage of the proposed control scheme is that more sophisticated battery charging and monitoring algorithms can be realized by using software control.

Fig. 5(a) shows the block diagram of the digital control scheme for the battery charger. The controller senses the inductor current and the output voltage to generate the PWM signal. The steady-state inductor current is equal to the battery charging current, therefore, the inductor current is sensed and closed-loop regulated for charging the battery. Multimode constant current charging scheme was adopted in the proposed dc UPS superscript [7].

PWM switching was selected at 80 kHz. The sampling frequency for the battery current loop is 20 kHz and that for the battery voltage loop is 5 kHz. A PI controller is used for both the voltage loop and a deadbeat controller is designed for the current loop.

Backup Mode If a power line failure is detected, the Q subscript 1 is turned off and the bidirectional dc-dc converter operates in discharge mode. Q subscript 3, D subscript 2, and L subscript u constitute a boost converter (Fig. 3c, on page 60). Fig. 5(b) shows the block diagram of the digital control scheme for the battery booster. The control of the boost converter requires a fast dynamic response to cope with the large load variations. Because the dc UPS may encounter a large load variation, the boost dc-dc converter must possess robust output voltage regulation either in CCM or DCM operating modes.

To achieve good robustness for voltage regulation, an inner current loop is also included. This boost converter is digitally controlled at a constant PWM switch frequency of 80 kHz. The sampling frequency for the battery current loop is 20 kHz, and the sampling frequency for the battery voltage loop is 5 kHz. To achieve fast dynamic response control of the boost converter, a deadbeat controller was designed for current loop.

API controller with nonlinear gain scheduling was used to regulate the voltage loop. The dc gain of the PI controller is compensated to achieve a guaranteed phase margin with maximum bandwidth under limited output voltage and current.

Experimental Results To verify the proposed DSP-controlled dc UPS, a prototype was built with the specifications listed in Table 2.

Specifications of some key components are listed in Table 3. Fig. 6 shows some simulation and experimental results of the DSP-controlled ac-dc converter. Fig. 6(a) and 6(d) are simulation and experimental results of the line voltage and current under a 50% load condition, and Fig. 6(b) and 6(e) are under a 50% load condition. Fig. 6(c) and 6(f) are simulation and experimental results of the output voltage, current, and line current under a 50% load transient.

Output voltage ripple of the ac-dc converter can't be over regulated by closed-loop control. However, a compromise can be made between PF and output voltage regulation. An increase of the output capacitance can reduce the output voltage ripple at the expense of higher cost and low-voltage loop bandwidth.

This work was supported by the National Science Council, Taipei, Taiwan - Project No. NSC 89-2213-F-009-131.

References 1. D. L. Cooper, "Standardization of specifications for distributed power converter modules," IEEE APEC Conf. Rec., Vol. 2, pp. 997-1003, 1996.

2. B. Moore, "SSI: building compliant power elements for servers," IEEE APEC Conf. Rec., pp. 23-27, 1999.

3. Y. S. Lee, K. W. Siu and B. T. Lin, "Novel single-stage isolated power-factor-corrected power supplies with regenerative clamping," IEEE Trans. Ind. Applications, Vol. 34, No. 6, pp. 1299-1308, Nov./Dec. 1998.

4. E. Rodriguez, D. Abud, and J. Arau, "A novel single-stage single-phase DC uninterruptible power supply with power-factor correction," IEEE Trans. on Ind. Electronics, Vol. 46, No. 6, pp. 1137-1147, Dec. 1999.

5. R. Redl, L. Balogh, and N. 0. Sokal, "A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage," IEEE PESC Conf. Rec., pp. 1137-1144, 1994.

6. S. Choudhury, "Implementing Triple Conversion Single-Phase online UPS using TMS320C240," Application Report SPRA589A, Texas Instruments, Sept. 1999.

7. Ying-Chuan Chiou and Ying-Yu Tzou, "Design and implementation of a multifunctional battery charging experimental system," 20th power conference of Taiwan, Taipei, Taiwan, pp. 7-12, Nov. 20-21, 1999.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.