Typically, dc-dc converters are designed for use at a fixed output voltage. Some applications, such as dual data rate (DDR) memory bus and other high-speed logic bus terminations, require the output voltage to be a fixed percentage of an external variable voltage source. These applications typically are high-performance designs requiring fast transient response and the ability to track an external voltage reference within close tolerances, as well as current source and sink capability.
Standard dc-dc converter solutions are not well equipped to meet these requirements. Most integrated solutions have an internal voltage reference that regulates the output voltage to a fixed dc value. To operate as continuous tracking regulator, the controlling device must allow for an external reference source to be used.
TI's TPS54×72 family of integrated dc-dc converters can be used to provide simple, low-cost solutions for designs when continuous tracking is required. The device features a REFINv pin that will override the internal voltage reference if it is below 1.75 V.
A common application requiring continuous voltage tracking is the termination supply, VTT, for DDR memory buses. For these DDR bus termination supplies, the VTT voltage generation circuit must be able to accurately track a reference voltage, Vref, which is 50% of the output supply voltage, VDDQ. This output voltage may vary by ±200 mV from its nominal value of 2.50 V. Additionally, VTT must remain within ±40 mV of Vref under all load and transient conditions.
In this application, the circuit generating VTT is able to sink current when the output buffer (line driver) is at a logic-high state and source current when the output buffer state is low. With the current-sinking mode, the current through the output inductor is reversed from the normal direction in a buck configuration. In the sinking mode, the switching process is similar to that of a boost converter, except the current flows into the output of the power supply gets boosted and flows out to the input supply rail. Control circuits such as the TPS54672 must function properly in both the buck and boost modes of operation.
The TPS54672 uses integrated, low on-resistance high- and low-side FETs operating in synchronous mode to achieve high efficiencies. This high level of integration also is important in reducing parts count and circuit size as the VTT termination circuit should be placed as close as possible to the parallel termination resistors to reduce the impedance and length of the signal return path.
For this design example, consider the schematic in Fig. 1. This circuit will derive an output voltage, VTT, from an input voltage of 3.3 V. The resistor divider network of R1 and R2 generates the REFIN voltage, which is 50% of the VDDQ voltage. To enhance performance, decoupling capacitors (C1 and C2) are placed in parallel with the resistor divider. Capacitors C4 and C5 provide input decoupling to the TPS54672. For proper operation, these parts are placed as close as possible to the VIN and PGND pins of the device.
The output filter in this circuit is composed of L1, C7 and C8. The minimum inductor value that can be used depends on the maximum allowable inductor ripple current. For a given set of operating conditions, smaller inductor values will have a larger ac ripple current. And because this ac current is all shunted to ground through the output filter capacitors, smaller inductor values will result in a relatively high output ripple voltage. However, smaller inductor values also will allow the output current to change more rapidly in response to load changes so the transient recovery will be better. The minimum inductor value is given by:
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. For designs using low-equivalent series resistance (ESR) output capacitors such as ceramics, a larger coefficient, KIND = 0.4, can be used. For this design, VOUT = 1.25 V, VIN(max) = 3.4 V, IOUT = 6 A, FSW(min) = 560 kHz. This results in a minimum inductor size of 5.88 µH, so L1 is chosen as 0.6 µH.
The important design factors for the output capacitor are dc-voltage rating, ripple-current rating and ESR. The dc-voltage and ripple-current ratings cannot be exceeded. The ESR is important because, along with the inductor current, it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist.
Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is desirable to keep the closed-loop crossover frequency at less than one-fifth of the switching frequency. With high switching frequencies, such as the 700-kHz frequency of this design, internal circuit limitations of the TPS54672 limit the practical maximum crossover frequency to about 70 kHz.
For this design, a 50-kHz closed-loop crossover is desired. To allow for adequate phase gain in the compensation network, the closed-loop crossover frequency should be at least three times the LC corner frequency for this design. Assuming typical placement of the compensation zeros, this limits the minimum capacitor value for the output filter to:
For LOUT = 0.6 µH and fCO = 50 kHz, the minimum value of COUT is approximately 150 µF. However, the low-value inductor will result in higher inductor ripple current; thus, low-ESR ceramic capacitors are used in the output filter. These capacitors keep the ripple voltage below 10-mV peak-to-peak and contribute to good transient response. Additionally, the output capacitors must be chosen to meet the transient response requirements. For rapid changes in load current, the initial current must be sourced or synced by energy stored in the output capacitor until the converter can ramp up or down the current through the inductor. The voltage change at the output can be approximated by:
Given that the output must not vary by more than ±40 mV, then for a 2-A step at a 1-A/µs slew rate, the use of 100-µF, low-ESR (2-mΩ) capacitors at C7 and C8 will result in a calculated voltage change of 22 mV.
In addition to the output filter, the other essential component to achieve good transient response characteristics is the compensation network in the feedback path. The high-unity-gain bandwidth (3-MHz minimum) and fast slew rate (1.4 V/µs) of the internal error amplifier permit the use of a high closed-loop crossover frequency of 50 kHz. Placement of the poles and zeros of the type-3 compensation network in this design are optimized for early phase boost below the output filter resonant frequency and a phase margin of 50 degrees at the closed-loop crossover frequency.
When responding to a 1.5-A to 4.5-A load-current step change with a slew rate of 0.1 A/µs, the peak voltage overshoot is measured at 30 mV, lower than the required ±40 mV. Larger load-current swings or extremely fast transient may require the use of more output-filter capacitance.
Load-urrent changes are not the only source of voltage tracking errors. The dc-dc converter circuit must be able to accurately track the supplied reference voltage, in this case one half of VDDQ. The TPS54672 can track reference voltages over the range of 0.2 V up to 1.75 V. Above 1.75 V, an internal reference voltage supercedes the voltage on the REFIN pin. Static tracking performance for the application circuit is shown Fig. 2.
The output voltage deviation is less than 4.5 mV from the REFIN voltage input over the entire range. Because the source of the REFIN reference voltage is itself a power supply voltage, load-current changes on the VDDQ bus may cause the VDDQ voltage and subsequently the REFIN voltage to change rapidly. The output of the tracking regulator is required to track this change as well.
Fig. 3 shows the response of the output voltage to an input step change. The VDDQ voltage was modulated with a 100-mV peak-to-peak square wave, resulting in a 50-mV peak-to-peak change at the REFIN pin. The output voltage tracks this change with an overshoot of approximately 30-mV and recovers within 80 µs.
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