As heat loads increase, the thermal management to keep junction temperatures within safe operating limits becomes more critical.
The data shows that the laminated copper patch method provides thermal performance on par with the best interface pad and exceeds most other insulating pads.
The trend in electronics is toward decreasing size and cost, while increasing speed, performance, and reliability. This results in increasing waste heat that must be removed from the operating devices. As heat loads increase, the thermal management to keep junction temperatures within safe operating limits becomes more critical. The drive for improved cooling efficiency requires optimization of not only the heat sink and the interface materials, but also the attachment method.
Attaching power semiconductors to heat sinks removes the waste heat that's generated in operation. A traditional method to provide the required electrical insulation is to attach these devices to heat sinks using mechanical fasteners, such as nuts and bolts or spring clips with either greased mica or thermally-enhanced silicone pads (Fig. 1, on page 60).
Another mounting method relies on insulated metal substrates (IMS), such as the Bergquist Company's IMS™, which allow the soldering of power devices. IMS is a laminate of aluminum carrier, a thermally-enhanced epoxy adhesive and a copper foil. In this method, you etch a panel of IMS material to create copper pads where the power devices are soldered. You then attach the assembly to a heat sink with mechanical fasteners or an adhesive tape.
An alternative method of soldering power devices to heat sinks involves the use of laminated copper. In this approach, you laminate a copper foil patch the size of the device to a heat sink using a bond film of thermally-enhanced Kapton MT film coated on both sides with thin layers of polyimide adhesive. You then solder the devices to the copper patches. You can laminate these copper patches to a variety of surfaces such as ribbed heat sinks — and as such, there's no need to attach them to a separate heat sink.
The evaluation of the thermal performance of these mounting techniques involved using TO-220 and TO-247 MOSFETS attached to heat sinks. To begin testing the performance, engineers powered the devices, recording the junction, case, sink, and ambient temperatures when reaching equilibrium. With the devices operating at constant power dissipation and powered to maintain 150°C junction temperature, an examination of the effect of forced convection took place.
Fig. 2, on page 61, shows the test fixture used for mechanical and laminated copper patch methods. Using a mechanical mounting technique, the engineers placed the power semiconductors on the appropriate interface pad, and torqued to the heat sink with a 4-40 nut and bolt to provide a nominal 300-psi mounting pressure. The next step was to stamp the heat sink from 0.125-in. thick aluminum with a 32.5 in.2 surface area and a natural convection thermal resistance of 5°C/W at 110°C. They allowed the fixture to relax for 1 hr before testing.
Fig. 3, on page 61, shows the test fixture used for the IMS and laminated copper patch techniques. This approach involves the use of a device attached to a 1.5-in.×1.5-in.×0.060-in. IMS board. After cutting the IMS board to size, the engineers masked a patch of copper in the center of the board to etch away the remaining copper. They soldered the appropriate device to the patch with solder paste in a Sikama reflow oven, sizing the patches 0.6 in.×0.8 in. for the TO-247 and 0.4 in.×0.6 in. for the TO-220. The laminated copper patch consisted of a 1 oz copper foil (1.4 mil thick) laminated with bond film (based on 1-mil Kapton MT with 0.15 mil of polyimide adhesive on both sides) to the stamped aluminum heat sink at 280°C at 500 psi for 30 sec. They sized the copper patches 0.6 in.×0.8 in. for the TO-247 and 0.4 in.×0.6 in. for the TO-220.
The testers measured junction temperatures using the electrical method with an Analysis Tech Phase 6 thermal analyzer [2,3] and calibrated the forward voltage of the source-drain diode, using it as the temperature-sensitive parameter. Using 36-gauge Type “T” thermocouples, they measured case, sink, and ambient temperatures. They also drilled wells 0.030 in. in diameter into the measured surface and the potted thermocouple into the wells with a thermally conductive silicone-potting compound.
After centering the test fixtures in the section of a 10-in. diameter wind tunnel, they powered the operation with the Phase 6 thermal analyzer. The engineers powered TO-220 and TO-247 MOSFETS to 8W and 15W dissipation, respectively, performing tests at natural convention 0 lfm and forced convention, 100 lfm air velocity, and measuring temperature at equilibrium.
Table 1, on page 60, describes the conventional insulating pads used in the mechanical attachment of devices to heat sinks.
These interface materials represent the broad range of materials available for use in mounting power semiconductors. The engineers compared their thermal performance against the laminated copper patch using a TO-220 and a TO-247 MOSFET. The two types of test performed were:
- Devices dissipated constant power, and testers recorded the junction temperature.
- Testers powered devices to a constant junction temperature and recorded dissipated power.
In the first test, the devices dissipated constant power and cooled them at two different air velocities. The TO-220 dissipated 8W, while testers set the TO-247 for 15W and used 0 lfm and 100 lfm air velocities.
Table 2 shows the corresponding junction temperatures and the junction-to-sink resistances (Rj-s) for the five interface materials and the laminated copper patch.
The data shows that the laminated copper patch method provides thermal performance on par with the best interface pad and exceeds most other insulating pads. An alumina-filled silicone sheet is widely used in commercial-grade power supplies. The data also shows that transitioning from this interface material to a laminated copper patch attachment method can reduce junction temperatures by 12°C to 17°C. This can be a significant reduction in the operating temperature of a power semiconductor.
Constant Junction Temperature
The next test involved increasing the power dissipation to the point where the junction temperature reached 150°C. Table 3 lists the dissipated power for each interface material and laminated copper patch method. The data supports the conclusion that the laminated copper offers improved thermal performance versus conventional interface systems.
The engineers compared the insulated metal substrate thermal performance to the laminated copper patch as follows: 1.5 in.×1.5 in. IMS substrates and laminated copper patches were prepared with TO-220 and TO-247 sized centered copper solder sites. The devices were soldered onto the patches and the test fixtures were attached to a pin fin heat sink with thermally conductive tape and the thermal tests of the previous section were repeated. You can see the resulting data in Tables 4 and 5.
These measurements report the thermal resistance from the junction to the aluminum plate of the IMS and the laminated copper. The data shows that the thermal performance of the IMS and the laminated copper is essentially the same. This doesn't take into account the fact that the IMS must be attached to a heat sink while the copper patch can be laminated directly to a heat sink. The additional thermal resistance of attaching the IMS to a heat sink is a variable to be considered.
The work presented here only addressed the thermal performance of the device attachment methods. Additional advantages of solder attachment such as reduced manual assembly, ability to be automated, reduced stress on the interface, and the increased reliability also need to be considered when selecting a power semiconductor mounting method.
Fraivillig, J., “The Optimal Passive Thermal Management”, 1-5, Proceedings of the 1999 International Systems Packaging Symposium, 1999.
Sofia, J.W., “Electrical Temperature Measurement using Semiconductors,” 23-25, Electronics Cooling, January 1997.
EIA/JESD51-1, “Integrated Circuits Thermal Measurement Method — Electrical Test Method (Single Semiconductor Device), EIA/JEDEC Standard.
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