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The design of low-cost consumer products like set-top boxes and DSL modems often requires a main logic supply in addition to the core voltage, so the power supply often provides multiple output voltages. Such multiple-output ICs include the MAX1864 (single buck switching regulator and two linear outputs), and the MAX1865 (single buck and four linear outputs). If you incorporate either of these ICs in your system and one of the linear outputs remains unused, you can further integrate the design by converting that linear-regulator capability into a watchdog timer (Figure).
R1 and C1 produce an RC time constant equal to the desired timeout period. Transistor Q1 and the passive components in its base circuit provide the watchdog's one-shot and reset functions. First, choose a watchdog timeout period and select R1 and C1. R1 can be calculated as follows:
If we let the timeout interval=100 ms, C1=0.47 µF, and VOUT=3.3 V, then R1=217 kΩ, the nearest standard value is 220 kΩ.
Q1 is a low-cost NPN bipolar transistor needed to discharge C1 during the timer's reset function. R2 and R3 maintain C2 in a zero-charge state, hold off Q1, and limit current into the base of Q1. R2 and R3 values are not critical, so they are set at 100 kΩ.
A value of 0.1 µF is selected for C2, which provides ac coupling (highly recommended) between the microcontroller and watchdog circuitry. Coupling ensures generation of the expected watchdog timeout when a locked-up microcontroller forces its output either low or high. (Without ac coupling, the timer may be disabled.) R5, R6 and C3 form a hysteresis network that prevents oscillation during the comparator transition.
A microcontroller must reset the timer before capacitor C1 charges to the 1.236-V threshold of the MAX1864/5. The control signal should normally be logic low, then assert a positive-going control pulse that returns to logic low in the inactive state. The pulse duration depends on the component values selected, but it only needs to ensure that C1 is discharged when the pulse terminates. To avoid the possibility of false timeouts with a 100-ms watchdog interval, the reset pulses should occur at maximum intervals of approximately 30 ms.