The active clamp transformer reset technique offers many welldocumented advantages over traditional singleended reset techniques, including lower voltage stress on the main MOSFET, the ability to switch at zero voltage, reduced EMI and duty cycle operation above 50%. Although the singleended forward converter is undeniably the most popular power topology using the active clamp, the same advantages can be applied to flyback converters.
Numerous publications have compared the performance advantages of the active clamp over the more widely used RCD clamp, third winding and resonant reset techniques. However, there are applicationspecific design considerations of how to best apply the active clamp for optimal circuit performance.
All papers written on the active clamp technique show the clamp circuit applied to either the high side directly across the transformer primary or the low side directly across the draintosource of the main MOSFET switch. Even more interesting, the authors seem to be equally divided as to which application — high side or low side — is best, while offering little or no explanation as to why.
There are subtle but noteworthy differences between applying the active clamp transformer reset technique to the high side and applying it to the low side. Each application results in a different transfer function, which in turn results in different voltages applied to the clamp circuit during reset. The value and voltage rating of the clamp capacitor is directly affected, as well as distinct considerations between gate drive circuitry for each case.
LowSide Clamp
Fig. 1 shows a lowside clamp applied to a basic singleended forward converter with a standard fullwave rectified output and LC filter. Whenever the main MOSFET, Q1, is conducting, the full input voltage is applied across the transformer magnetizing inductance. This is referred to as the power transfer mode.
Conversely, whenever the auxiliary (AUX) MOSFET, Q2, is conducting, the difference between the clamp voltage and the input voltage is applied across the transformer magnetizing inductance. This is referred to as the transformer reset period. Specific to the lowside clamp is the fact that the auxiliary MOSFET, Q2, must be a Pchannel device only because of the direction of the bodydiode.
Also note Q2 carries only the transformer magnetizing current, which has a very small average value compared to the reflected load current. For this reason, specifying a low gate charge MOSFET should be a primary consideration, with low R_{DS(ON)} being only a secondary concern.
An additional deadtime period is introduced between the turn on and turn off transitions of Q1 and Q2. During the deadtime, primary current flow remains continuous through the bodydiode of either the Pchannel AUX MOSFET, Q2, or the main MOSFET, Q1. This is commonly known as the resonant period in which the conditions are set for zero voltage switching (ZVS). Although this is an important and unique characteristic of the active clamp topology, it's of little importance for this comparison, other than it always exists whether the active clamp is applied to the low side or the high side.
Neglecting the effect of leakage inductance, the transfer function for the lowside clamp can be derived by applying the principle of voltseconds balance across the transformer magnetizing inductance.
where D is the duty cycle, V_{IN} is the input to the clamp circuit, and V_{C(LS)} is the clamp voltage. Simplifying (1) for the clamp voltage gives:
Note that the transfer function given in (2) is also the same transfer function for a nonisolated boost converter, and this is why the lowside clamp is commonly referred to as a boosttype clamp.
The result of (2) gives an expression for the transfer function between the input voltage and the clamp voltage. However, notice from Fig. 1 that whenever Q2 is conducting, the clamp voltage is applied directly across the draintosource junction of Q1 and not the transformer primary magnetizing inductance. Therefore, (2) can be extended and written to include an expression for determining the draintosource voltage stress on the main MOSFET, Q1:
During the transformer reset period, the dot polarity on the transformer primary reverses, so the voltage applied to the primary is now defined as:
If the expression for V_{C(LS)} from (2) is substituted into (4) and simplified, a transfer function relating the input voltage to the reset voltage can be shown as:
Furthermore, the duty cycle, D, of a singleended forward converter is defined as the ratio of the output voltage to the input voltage multiplied by the transformer turns ratio, N.
Substituting (6) into (3) and (5) and simplifying gives expressions for V_{C(LS)} and V_{RESET(LS)} in terms of V_{IN}, V_{O} and N, as shown in (7) and (8).
The results of (7) and (8) now can be used to graphically show how the clamp voltage and transformer reset voltage vary with input voltage for a fixed value of V_{O} and a fixed transformer turns ratio, N. Using a value of 4 V for V_{O} (3.3 V plus some additional voltage drop), the graphical results of (7) are first plotted in Fig. 2 and shown for various transformer ratios, N.
From Fig. 2, notice the drastic variation in MOSFET voltage stress during minimum input voltage (maximum duty cycle, D). For this reason, a PWM controller, such as the UCC2891 shown in Fig. 4, must provide the capability of precisely limiting the maximum duty cycle. The consequence could be destructive voltage levels applied to the MOSFET or having to over specify the maximum MOSFET voltage rating.
From an active clamp design standpoint, it's helpful to begin the power stage design by plotting the graph shown in Fig. 2. A transformer turns ratio can then be selected to yield a relatively constant V_{DS(LS)} at each of the input voltage extremes. Fig. 2 shows that, for a typical forward converter operating over the full telecom input voltage (36 V < V_{IN} < 75 V), a turns ratio of N = 6 results in 110 V of applied draintosource voltage at V_{IN} = 36 V and V_{IN} = 75 V.
The MOSFET voltage shown in Fig. 2 also is the voltage seen by the clamp capacitor, C_{cl}. As such, the clamp capacitor must be appropriately chosen to withstand the full clamp voltage plus any additional derating voltage. Having chosen a turns ratio of 6, the transformer reset voltage, V_{RESET(LS)}, given by (8) also can be plotted against varying input voltage (Fig. 3).
Gate Drive Considerations for LowSide Clamp
Because it has already been established that the auxiliary MOSFET of a lowside clamp circuit must be a Pchannel device, a negative gate drive voltage is required to turn this device on fully. However, most pulsewidth modulator (PWM) controllers or gate drive ICs don't produce outputvoltage levels below ground reference. Using a gate drive circuit applied to a lowside clamp, such as the one shown in Fig. 4, the Pchannel MOSFET can be directly driven from a lowside referenced driver or PWM gate drive signal.
Whether derived directly from a PWM or from a gate driver IC, the gatetosource voltage of Q1, V_{OUT}, must be synchronously in phase with V_{AUX}, as shown in the timing diagram (deadtime delays not shown) of Fig. 4. Using an advanced PWM controller such as the UCC2891 simplifies the task of driving both MOSFET switches. Along with an internal ±2A drive, userprogrammable dead time and a precise maximumdutycycle clamp, the UCC2891 provides the exact phasing and control specifically intended for lowside active clamp applications.
The first time the PWM gate voltage, V_{AUX}, goes positive, the diode, D1, will be forward biased and the capacitor, C1, will be charged to V_{AUX} volts. The capacitor voltage then discharges through R1. If the time constant of R1 and C1 (see Equation 9 and Fig. 4) is much greater than the PWM period, then the voltage across C1 remains relatively constant and the resultant gate to source voltage seen at Q2 is V_{AUX} with a peak positive value of zero volts. Therefore, V_{AUX} is effectively shifted below ground and is now adequate for driving the gate of the Pchannel MOSFET, Q2.
where F_{PWM} is the switching frequency.
Parameter  HighSide Clamp  LowSide Clamp 

V_{DS}  
V_{RESET}  
V_{C}  
C_{cl} (applied voltage)  • Lower voltage by V_{IN} volts • Highest V_{cl} occurs at D_{MAX} • Careful attention for wide V_{IN} applications  • Higher voltage by V_{IN} Volts • Transformer turns ratio critical at for limiting V_{cl} • Careful attention for highvoltage dcdc applications 
C_{cl} (component value)  • Same value as low side for given ripple voltage  • Same value as high side for given ripple voltage 
AUX MOSFET  NChannel  PChannel 
Gate Drive  • Gate drive transformer required • AUX MOSFET V_{GS} out of phase with main MOSFET V_{GS} — UCC2893 PWM controller  • Simple RCD clamp gate drive • AUX MOSFET V_{GS} in phase with main MOSFET V_{GS} — UCC2891 PWM vontroller 
HighSide Clamp
Fig. 5 shows a highside clamp applied to the same basic singleended forward converter shown in Fig. 1. Similar to the lowside clamp, whenever the main MOSFET, Q1, is conducting, the full input voltage is applied across the transformer magnetizing inductance, which is referred to as the power transfer mode. Whenever the auxiliary MOSFET, Q2, is conducting, the clamp voltage, V_{C(HS)} is applied directly across the transformer magnetizing inductance, referred to as the transformer reset period. This is quite different than the lowside case where the clamp voltage, V_{C(LS)}, was applied directly across the draintosource junction of the main MOSFET.
The highside clamp auxiliary MOSFET, Q2, must be an Nchannel device only because of the direction of the bodydiode. Similar to the lowside clamp circuit, the dominant losses in Q2 are gate charge and switching losses; thus, a MOSFET is chosen with the same lowgatecharge considerations in mind.
Neglecting the effect of leakage inductance, the transfer function for the highside clamp can be derived, once again, by applying the principle of voltseconds balance across the transformer magnetizing inductance.
Simplifying (10) for the clamp voltage, V_{C(HS)}, gives:
Note that the transfer function given in (11) is the same transfer function for a nonisolated flyback converter, which is why the highside clamp is commonly referred to as a flybacktype clamp.
The result of (11) gives an expression for the transfer function between the input voltage and the clamp voltage. However, notice from Fig. 5 that whenever Q2 is conducting, the clamp voltage is applied directly across the transformer primary magnetizing inductance. Therefore, (11) can be extended and written to include an expression for determining the reset voltage:
During the transformer reset period, the dot polarity on the transformer primary reverses, so the voltage applied to draintosource of the main MOSFET, Q1, can be written as:
If the expression for V_{C(HS)} from (11) is substituted into (13) and simplified, a transfer function relating the input voltage to the main MOSFET draintosource voltage can be shown as:
Substituting (6) into (12) and (14) and simplifying gives expressions for V_{RESET(HS)} and V_{C(HS)} in terms of V_{IN}, V_{O} and N, as shown in (15) and (16).
The results of (15) now can be used to graphically show how the clamp voltage and transformer reset voltage vary with input voltage for a fixed value of V_{O} and a fixed transformer turns ratio, N. Using the same previous value of 4 V for V_{O} (3.3 V plus some additional voltage drop), the graphical results of (15) are plotted in Fig. 6 and shown for various transformer ratios, N.
Since the MOSFET draintosource voltage given by (16) is identical to the lowside clamp, V_{DS(LS)}, given by (7), the graphical result for (16) can also be represented by Fig. 2.
Gate Drive Considerations for HighSide Clamp
Unlike the lowside clamp circuit of Fig. 4, the highside clamp makes use of an Nchannel auxiliary MOSFET. Assuming the PWM controller doesn't have an internal highside driver stage, a 1:1 gate drive transformer configured as shown in Fig. 8 can be used. For highside active clamp circuits, the gatetosource voltage of Q1, V_{OUT}, must be asynchronously out of phase with V_{AUX}, as shown in the timing diagram (deadtime delays not shown) of Fig. 8.
The UCC2893 active clamp PWM controller is electrically and functionally equivalent to the UCC2891 shown in Fig. 4 with one exception: where the UCC2891 is intended for lowside active clamp circuits, the UCC2893 provides the exact phasing and control specifically intended for highside active clamp applications. Therefore, the V_{AUX} output of the UCC2893 is out of phase with the V_{OUT} output, as shown in the timing diagram of Fig. 8.
Clamp Capacitor Selection
Whether using a highside or lowside active clamp circuit, the voltseconds applied to the transformer primary must balance, making the transformer reset voltage equal for each case. And because the primary MOSFET draintosource voltage stress and transformer reset voltage are the same for each circuit, it's the varying clamp voltage applied across the clamp capacitor, C_{cl}, that must be considered. The details of the clamp capacitor voltage variations can be seen by comparing the difference between the clamp voltage transfer functions for each case.
Substituting (2) and (11) into (17), ΔV_{C} can be written as:
The result of (18) shows that V_{C(LS)} is greater than V_{C(HS)} by V_{IN} volts. Considering the range of V_{IN} to be 36 V < V_{IN} < 72 V, a graphical comparison of V_{C(HS)}, V_{C(LS)} and ΔV_{C} is shown in Fig. 7.
Therefore, the first consideration for sizing the clamp capacitor is to know what the appropriate voltage rating should be over a given range of V_{IN}. The graph in Fig. 7 shows that ΔV_{C} linearly increases with V_{IN}. For higher values of V_{IN}, the highside clamp offers the lowest voltage stress. However, the capacitor must still be selected based upon the rising clamp voltage seen at minimum V_{IN}, maximum D, which is about 80 V for this example.
The value of the clamp capacitor primarily is chosen based on the amount of allowable ripple voltage that can be tolerated. Also, it's assumed the value of the capacitor is large enough to approximate the clamp voltage as a constant voltage source. However, according to (2) and (11) V_{cl} changes with input voltage.
Whenever a line transient or sudden change in duty cycle is commanded, it takes a finite amount of time for the clamp voltage, and therefore the transformer reset voltage, to adapt. Larger capacitor values result in less voltage ripple but introduce a transient response limitation. Smaller capacitor values result in faster transient response, at the cost of higher voltage ripple.
Ideally, the clamp capacitor should be selected to allow some voltage ripple, but not so much as to add additional draintosource voltage stress to the main MOSFET, Q1. Allow approximately 20% voltage ripple while paying close attention to V_{DS} of Q1.
A simplified method for approximating C_{cl}, is to solve for C_{cl}, such that the resonant time constant is much greater than the maximum offtime. Although additional factors such as the power stage time constant and control loop bandwidth also affect transient response, this approach, stated in (19), assures transient performance isn't compromised — at least from the active clamp circuit point of view.
where L_{mag} is transformer magnetizing inductance and t_{OFF(MAX)} is the maximum offtime.
By dividing both sides of (19) by the total period, T, and solving for C_{cl}, (19) can be rewritten as (20), expressing C_{cl} in terms of known design parameters:
Once C_{cl} is calculated by (20), the final design value may vary slightly after the clamp capacitor ripple voltage is measured in circuit. Furthermore, (20) is valid for both the highside and lowside active clamp circuit. Thus, for a desired clamp ripple voltage, the clamp capacitor component value will be the same for each case.
There are similarities as well as subtle but important differences between applying the active clamp circuit to the high side versus the low side. A direct comparison between the differences and similarities is summarized for each circuit in the table.
The draintosource voltage stress, V_{DS}, on the main MOSFET and the transformer reset voltage, V_{RESET}, are the same for both circuits. The differences between the clamp voltage transfer functions may seem minor, but each has a significant effect on the clamp capacitor selection and transformer turns ratio.
For singleended power converter applications requiring the absolute lowest voltage stress on the clamp circuit, the highside clamp is the best choice. Even though the highside clamp produces a lower overall clamp voltage, the voltage tends to rise more sharply at minimum V_{IN}, maximum duty cycle. Therefore, specific attention must be paid to accurately limit the maximum allowable duty cycle so that the maximum V_{DS} of the main MOSFET isn't exceeded.
The highside clamp uses an Nchannel AUX MOSFET, so more component choices are available than the lowside clamp using a Pchannel device. However, the highside clamp circuit requires a gate drive transformer, which may come into play when absolute low cost is a primary concern.
Compared to the highside counterpart, the lowside clamp yields a slightly higher but better controlled clamp voltage when the transformer turns ratio is properly selected, according to Fig. 2. The gate drive circuit for the lowside clamp AUX MOSFET also is simpler, because a gate drive transformer isn't required. When the input voltage range is 2:1 or greater, the lowside clamp is a good choice, because a higher duty cycle can be tolerated with less variation in clamp voltage.
Whether a highside or lowside clamp is applied, the efficiency and performance benefits are huge compared to the betterknown RCD clamp and resonant reset techniques. With the advantage and flexibility of advanced PWM controllers, such as the UCC2891 family, the complexities normally with implementing active clamp transformer reset are greatly simplified.
References

Andreycak, Bill. “Active Clamp and Reset Technique Enhances Forward Converter Performance,” Power Supply Design Seminar SEM1000, Topic 3, Texas Instruments Literature No. SLUP108.

Dalal, Dhaval. “Design Considerations for Active Clamp and Reset Technique,” Power Supply Design Seminar SEM1100, Topic 3, Texas Instruments Literature No. SLUP112.

Mappus, Steve. “UCC2891EVM, 48V to 3.3V, 30A Forward Converter with Active Clamp Reset,” User Guide to Accommodate UCC2891EVM, Texas Instruments Literature No. SLUU178.

Mappus, Steve. “Designing for High Efficiency with the UCC289/1/2/3/4 Active Clamp PWM Controller,” Application Note, Texas Instruments Literature No. SLUA303.
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