The LTC4366 protects against surges by controlling the gate of an external N-channel MOSFET so that it can absorb the surge and protect the loads. Normally, the IC and MOSFET allow the power supply to service its loads with minimal insertion loss. However, if the power supply input receives a surge voltage, the LTC4366 (Fig. 1) and MOSFET clamp the voltage applied to the loads to protect from damage or failure. It is intended for automotive, avionic and industrial applications with an operating temperature range of -40oC to +150oC.
An RSS resistor in its return line (VSS) isolates the LTC4366 and allows it to float up with the system supply input (VIN). Thus, the LTC4366 protects systems that continuously operate above 100V, or require protection from extremely high voltage transients (>200V). Its topology, external MOSFET, and external voltage dropping resistor (RSS) allow it to float. The upper voltage protection limit depends on the RIN resistor value and the selected MOSFET’s ability to handle the power dissipated during an input voltage surge. As an example, Fig. 2 shows a 250V input surge and the corresponding clamped output produced by the LTC4366 circuit.
This floating topology allows the LTC4366 to operate from 9V to >500V inputs. Its adjustable, well-regulated output clamp voltage provides flexibility to control the clamped output voltage level without affecting system operation. This lowers costs for low voltage applications, because it eliminates the need for high-voltage rated components downstream.
There are two LTC4366 versions that differ in their response to faults. After a fault, the LTC4366-1 latches off while the LTC4366-2 will auto-retry. The LTC4366-1 and MOSFET will remain off after a fault until the S—D pin is toggled low and then high. After clearing the fault, the LTC4366-1 GATE turns the MOSFET on again. In contrast, the LTC4366-2 waits 9 seconds, then automatically clears the fault and restarts. During a fault, strong sink current pull-down (>150mA) on the GATE pin ensures fast response time.
An adjustable fault timer limits power dissipation in the external MOSFET. During a fault it uses a current source to charge the capacitor (CT) on the TIMER pin (Fig. 1), which allows use of lower rated SOA (safe operating area) MOSFETs. Inrush current limiting eliminates current spikes propagating through the MOSFET to the output during power-up by controlling the GATE pin slew rate.
When shut down,the LTC4366 turns off the MOSFET by tying the GATE and OUT pins together with a switched resistor to reduce current consumption to less an 20µA. In automotive applications, the low shutdown current minimizes the battery’s discharge when parked for long periods. Also, it offers additional power savings for improved battery life in portable applications.
The LTC4366 has three operating modes: start, run and regulate (the surge). In run and regulate modes, the IC receives most of its power from the output, so the MOSFET isolates the surge from the IC’s power pins. This allows surge voltages up to the breakdown voltage of the external MOSFET.
In the start mode, a 15μA trickle current flows through RIN, with half used to charge the gate with the other half used as bias current. As the GATE pin charges, the external MOSFET brings up the OUT pin. This leads to the run mode where the output is high enough to power a charge pump that operates the MOSFET’s gate 12V above its source voltage.
Once the LTC4366 is powered up, it is ready to protect the load against an overvoltage transient. This is accomplished in the regulate mode with an overvoltage regulation amplifier, referenced to a 1.23V source. If the voltage drop across the upper feedback resistor, RFB1, exceeds 1.23V, the regulation amplifier pulls the gate down to move the RFB1 voltage back to 1.23V. This allows the ratio of RFB1/RFB2 to set the clamp voltage.
During surge regulation, the excess voltage is dropped across the MOSFET. To prevent overheating the MOSFET, the LTC4366 limits the overvoltage regulation time using an internal timer connected to the TIMER pin. The TIMER is charged with 9μA until the pin exceeds 2.8V. At that point it sets an overvoltage fault, the MOSFET turns off, and the IC enters a 9 second MOSFET cool-down period. During cool-down, the GATE pin voltage is pulled to the OUT pin.
At the beginning of start-up, during shutdown, or after an overvoltage fault, the GATE pin is clamped to the OUT pin, thereby shutting off the MOSFET. This allows the VSS and OUT pins to be pulled to ground by the output load and RSS. Under this condition the VDD pin is clamped with a 12V shunt regulator to VSS. The full supply voltage minus 12V is then impressed on RIN, which sets the shunt current. The shunt current can be as high as 10mA - several orders of magnitude higher than the typical 9μA VDD pin quiescent current.
Normally, the external MOSFET is fully on, powering the load with very little voltage drop. As the input voltage increases, the OUT voltage also increases until it reaches a regulation point (VREG). From that point, any further voltage increase is dropped across the MOSFET. The MOSFET is still on, so the LTC4366 allows uninterrupted operation during a short overvoltage event.
The LTC4366 includes two shunt regulators coupled with the external voltage dropping resistors, RSS and RIN, to generate internal supply rails at the VDD and OUT pins. These shunt-regulated rails enable overvoltage protection from unlimited high voltage transients, regardless of the voltage rating of the LTC4366’s internal circuitry.
When the output is at the VREG regulation point a timer starts, preventing excessive MOSFET heating. Normally, the TIMER pin is held low with a 1.8μA pull-down current. During regulation, the TIMER pin charges with 9μA. If the regulation point is held long enough for the TIMER pin to reach 2.8V, the IC generates an overvoltage fault.
After an overvoltage fault, the IC allows the FET to cool down and self-starts (LTC4366-2), or remains latched off until the S—D pin activates a shutdown followed by a start-up command (LTC4366-1). The nine second cool-down allows a very low pulsed power duty cycle.
The proper rating for the RSS resistor (Fig. 1) is an important consideration. During an overvoltage event, the OUT pin is at the regulation voltage (VREG), and the voltage across RSS is VREG minus 5.7V. Large differences between minimum supply voltage and the regulation voltage may require a high wattage RSS.
The full supply voltage minus 12V can appear across RIN during overvoltage cool-down. Normally, RIN is several times larger than RSS, reducing RIN’s power and size requirements.
The external MOSFET’s important parameters are:
- On-resistance (RDS(ON))
- Maximum drain-source voltage (V(BR)DSS),
- Threshold voltage
The maximum allowable drain-source voltage must be higher than the supply voltage. If the output is shorted to ground or during an overvoltage event, the full supply voltage appears across the MOSFET. Applications with supplies less than 12V require a logic-level MOSFET, whereas a standard threshold MOSFET is sufficient above 12V.
The SOA of the MOSFET must encompass all fault conditions. In normal operation, the MOSFET is fully on, dissipating very little power. High voltage drop across the MOSFET can occur in these cases. For reliable operation, consider the MOSFET SOA curves along with selection of the fault timer capacitor (CT) that controls cool-down.
High impedances of the S—D, VDD, and GATE pin circuits make them susceptible to ground leakages. For example, a leakage to ground on S—D will activate the shutdown mode if it is over 1.6μA. Therefore, provide adequate spacing away from grounded traces and add conformal coating to exposed pins, which lowers the risk of leakage current.
It is important to put bypass capacitor, C1, as close as possible to the OUT and VSS pins. The RG resistor should be close to the MOSFET’s gate pin, which limits parasitic trace capacitance that can cause MOSFET self-oscillation.
The FB pin is sensitive to parasitic capacitance when the regulation loop is closed. One result from this capacitive loading is output oscillations during overvoltage regulation. For best results, place resistors RFB1 and RFB2 close to the FB pin and minimize PCB traces leading to that pin.
High Voltage Application
The circuit in Fig. 3 accepts 110VAC (rectified to 160V) and protects the load from accidental connection to 220VAC by limiting the output to less than 200V. The circuit has a 100V to 800V VIN operating range where the MOSFET breakdown voltage limits the maximum input voltage. An internal charge pump has a 0.47μF bypass capacitor (C1) that provides good noise immunity from voltage transients.
28V Vehicle Application
The circuit shown in Fig. 4 provides reverse voltage protection for an automotive application. There are three modes to this circuit:
- MOSFET turn on when the input is 18V to 41V
- Output clamp to 43V when more than 43V appears at the input
- Reverse voltage protection when up to –250V DC is present at the input
Circuitry in Fig. 4 (dotted box) provides reverse voltage protection. When a positive voltage is first applied to the input, D3 and the forward biased base-collector junction of Q2 allow the gate of M2 to follow the input voltage minus a two diode drop. The body diode of M2 transmits power to the LTC4366. Once powered up, the LTC4366 enhances the gate of M1 and M2. The M1 and M2 MOSFETs provide a low impedance path to the load. During overvoltages, D1 blocks excessive positive voltage from the input supply passing to the LTC4366's GATE. D4 eliminates current flow through R6 when the input is positive. D3 prevents emitter base breakdown of Q2 when the input is powering up. During negative input voltages, Q2 turns on when current from R6 develops a forward diode drop on R5. Q2 holds the gate of M2 at the input voltage that turns M2 off.
High Voltage Surges
Automotive, industrial and avionic applications commonly encounter high voltage power supply spikes with durations ranging from a few microseconds to hundreds of milliseconds. System electronics must survive these transient voltage spikes and also reliably ride through the event.
When long wires distribute power, severe transients can generate load steps (abrupt changes in load current). Negative load steps happen when load current drops from a high to a low value. Negative changes in current (dI/dt) cause the wire’s parasitic inductance to generate a positive-going high voltage spike that can damage neighboring devices on the same wire.
Fast load switching by relays, switch contacts and solid state load switching produce high dI/dt. Corroded connections between a power source and load can lead to an abrupt current interruption and a high dI/dt. For example, automotive load dumps occur where there is a sudden break in the battery connection caused by vibration and corroded terminals.
Load dump causes a voltage surge that stays elevated for hundreds of milliseconds, as shown in Fig. 5. According to the Society of Automotive Engineers (SAE), the transient may be as high as 125V. A typical load dump profile has a rise time of 5 ms, and decaying exponentially with a time constant of 200ms. Regeneration in solenoids and motors can cause similar events in industrial systems.
These transients pose a difficult challenge for designers trying to protect sensitive electronics. This protection has been achieved using bulky capacitors, TVS diodes and fuses, but discrete solutions consume a lot of real estate. An improved approach is the use of an IC like the LTC4366, that is specifically intended to clamp input voltages and protect against surges and transients.