Commercial GaN power devices can’t handle voltages above about 600 volts, however, which limits their use.
“Virtually all commercially available GaN power semiconductors are lateral devices,” says Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories, and senior author on a new GaN paper. “So we fabricate the entire lateral device on the top surface of the GaN wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor.”
Palacios listed the drawbacks of lateral GaNFETs:
1. Device dimensions (and cost) increase with breakdown voltage
2. Maximum current limited by routing of wiring
3. Very non-uniform heat generation and dissipation
4. Surface states cause dynamic on resistance and current collapse
5. Difficult to make a normally-off device
6. High leakage current
7. High electric field near surface and numerous interfaces reliability issues
8. Lack of avalanche breakdown
9. Same semiconductor for access regions and drift region
“Vertical devices are much better in terms of how much voltage they can manage and how much current they control,” Palacios explains. “Current flows into one surface of a vertical device and out the other. That means that there’s simply more space in which to attach input and output wires, which enables higher current loads.” Palacios pointed out some advantages of vertical GaNFETs:
1. Device dimensions (and cost) roughly independent of breakdown voltage
2. Vertical current extraction >100 A possible
3. Uniform heat generation and dissipation
4. Reduced dynamic on resistance and current collapse
5. New flexibility for normally-off device technology
6. Ultra-low leakage current
7. Potentially better reliability as E-field far from surface
8. Avalanche breakdown demonstrated
9. Drift region could be graded for optimum critical field
At a recent IEEE International Electron Devices meeting, researchers from MIT, semiconductor company IQE, Columbia University, IBM, and the Singapore-MIT Alliance for Research and Technology, presented a new design that, in tests, enabled GaN power devices to handle voltages of 1,200 volts.
That’s already enough capacity for use in electric vehicles, but the researchers emphasize that their device is a first prototype manufactured in an academic lab. They believe that further work can boost its capacity to the 3,300-to-5,000-volt range, to bring the efficiencies of gallium nitride to the power electronics in the electrical grid itself. That’s because the new device uses a fundamentally different design from existing gallium nitride power electronics.
Palacios notes that, “with lateral devices, all the current flows through a very narrow slab of material close to the surface. We are talking about a slab of material that could be just 50 nanometers in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”
Although their advantages are well-known, vertical devices have been difficult to fabricate in GaN. For efficient switching, the current flowing through the semiconductor needs to be confined to a relatively small area, where the gate’s electric field can exert an influence on it. In the past, researchers had attempted to build vertical transistors by embedding physical barriers in the GaN to direct current into a channel beneath the gate.
But the barriers are built from a temperamental material that’s costly and difficult to produce, and integrating it with the surrounding GaN in a way that doesn’t disrupt the transistor’s electronic properties has also proven challenging. Among the other challenges are:
· High dislocation density in bulk temperamental materials
· High leakage current
· Difficulties in activating the buried p-type GaN materials
· Difficulties in multiple material regrowth
Palacios and his collaborators adopted a simple but effective alternative. The team includes first authors Yuhao Zhang, a postdoc in Palacios’s lab, and Min Sun, who received his MIT PhD in the Department of Electrical Engineering and Computer Science (EECS) last spring; Daniel Piedra and Yuxuan Lin, MIT graduate students in EECS; Jie Hu, a postdoc in Palacios’ group; Zhihong Liu of the Singapore-MIT Alliance for Research and Technology; Xiang Gao of IQE; and Columbia’s Ken Shepard.
Rather than using an internal barrier to route current into a narrow region of a larger device, they simply use a narrower device. Their vertical gallium nitride transistors have bladelike protrusions on top, known as “fins.” On both sides of each fin are electrical contacts that together act as a gate. Current enters the transistor through another contact, on top of the fin, and exits through the bottom of the device. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off. Fig. 1 shows construction of this vertical GaN power FET.
“Yuhao and Min’s brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,’” Palacios says. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”
This work has been partially funded by the ARPA-E SWITCHES program, and made possible through collaborations with Prof. Kenneth Shepard’s group at Columbia University, Ming Pan and Xiang Gao from IQE and Devendra Sadana and Stephen Bedell from IBM Research.
ARPA-E's SWITCHES program (Strategies for Wide-Bandgap, Inexpensive Transistors for Controlling High-Efficiency Systems) is focused on developing next-generation power switching devices that could dramatically improve energy efficiency in a wide range of applications. ARPA-E Projects at Columbia University and Avogy are involved with research on vertical GaN devices.
Columbia University and its project partners, MIT, IBM and IQE, are also working on developing vertical GaN devices using a technique called spalling, which involves exfoliating a working circuit and transferring it to another material. They will spall and bond entire transistors from high-performance GaN wafers to lower cost silicon substrates. Substrates are thin wafers of semiconducting material needed to power devices like transistors and integrated circuits. GaN substrates operate much more efficiently than silicon substrates, particularly at high voltages, but the high cost of GaN is a barrier to its widespread use. The spalling technique developed by Columbia and its project partners will allow GaN substrates to be reused, lowering their manufacturing cost. If successful, their approach would facilitate low-cost, high-power GaNFETs.
Researchers at Avogy (San Jose, Ca) have been developing a vertical GaN transistor that is said to be 30 times smaller than conventional silicon transistors but can conduct significantly more electricity. Avogy's vertical device architecture can also enable higher current devices. Avogy projects it will achieve functional cost parity with conventional silicon transistors within three years, while offering game-changing performance improvements. If successful, Avogy's transistors will enable smaller, more energy-efficient, more reliable, and more cost-effective high-power converters. There is now some question as to whether Avogy is still a viable company.