Power Electronics

Online Design Tool Programs Interleaved PFC

Using a traditional multiplier approach, Analog Devices’ ADP1048 implements an average current mode power factor correction controller. It converts all signals from analog to digital before they are processed by the control loop. The ADP1048 stores all possible digital operating parameters in registers and in an EEPROM. This allows a designer to select those parameters required for a specific application, which involves programming the ADP1048. You can program the IC manually, or use an online GUI (graphical user interface) design tool that simplifies the task for power electronics engineers.

To understand how the ADP1048, works we have to look at its operation in detail. It uses Σ-Δ ADCs for high performance, analog-to-digital converters (ADCs). Converting to the digital domain provides maximum flexibility, and allows all key parameters to be reported and adjusted by its PMBus™ interface.

An internal EEPROM stores all programmed values and provides the ability to set operating parameters. Two major blocks partition the 8k x 8 EEPROM. The INFO block contains 128 8-bit bytes. The main block contains 8K 8-bit bytes partitioned into 16 pages of 512 bytes each.

The ADP1048 operates from a single 3.3 V supply. It is housed in a 24-lead QSOP package specified for operation over a −40°C to +85°C ambient temperature range.

Fig. 1 shows a typical interleaved application for the ADP1048. The IC has a dedicated circuit to maintain current balance in each interleaved phase (Fig. 2). This ensures that each interleaved phase provides equal power regardless of the tolerance of the inductor and the boost switch driving circuitry. Using the IBAL pin, the current balancing circuit monitors the current flowing in both switches of the interleaved PFC topology and stores this information.

The IC can operate in a bridgeless boost configuration because it provides separate drivers for the two external N-channel power MOSFETs. This circuit removes diode conduction losses caused by the input bridge rectifier in the traditional PFC circuit.

Current and VOLTAGE Sensing

A key function of the ADP1048 is sensing current to control, protect, and monitor the PFC. Normally, the power factor correction control loop obtains inductor current information using a sense resistor on the input bus with differential inputs to a current sense ADC (Fig. 3). And, a pair of matched current sources level shift the negative signal across the current sense element in the input range of the current sense ADC.

Voltage sensing, shown in Fig. 4, also controls, protects, and monitors the PFC stage. Input and output voltages are sensed using dedicated ADCs. And, you can calibrate voltage sense digitally to remove any errors caused by external components. The sense point on the power rail requires an external resistor divider to bring the signal within the ADCís operating input range (0 V to 1.6 V). This scaled-down signal is fed into a high speed Σ-Δ ADC.

The VFB pin controls, monitors, and protects the output voltage. VFB is also the main feedback loop for the power supply. It requires an external resistor divider to bring the signal within the operating input range of the ADC (0 V to 1.6 V). This scaled-down signal is fed into a high speed Σ-Δ ADC.

In the bridgeless boost operation mode, during the positive ac line phase, only one boost stage is effectively working. The second one is passive, and the current flows in Q2 from the source to the drain. Turning the Q2 FET fully on during this phase allows conduction losses in Q2 to be minimized.

When the ac line phase becomes negative, the roles of Q1 and Q2 are reversed, and Q2 actively switches while Q1 is always on. The phase information is detected from the ac line via the IBAL pin.

Pulse-Width Modulation (PWM)

The ADP1048 can implement either a leading edge or trailing edge PWM. Trailing edge modulation is the more popular modulation scheme. Using trailing edge modulation, the rms ripple current in the bulk capacitors can be reduced when used with downstream converter synchronization.

The ADP1048 allows the user to program the minimum off time and the minimum on time for the PWM outputs separately, thereby setting minimum and maximum duty cycles. Minimum off time represents the minimum time that the PWM is low during each switching cycle. You can program it from 40 ns to 1.2 μs in steps of 80 ns. Therefore, the maximum duty cycle can be clamped between 96% and 99.8% at the minimum frequency and between 48.8% and 96.8% at the maximum frequency. The minimum on time is the smallest PWM pulse that the modulator generates on the PWM output. It can be programmed from 0 ns to 1200 ns in steps of 80 ns.

The PWM signal can be altered digitally to optimize for EMI reduction. For a wider but lower EMI spectrum, the switching frequency varies with the rectified line voltage. The switching cycle changes linearly with time from 87.5% to 112.5% of the nominal value, resulting in a frequency variation of 114% to 89% of the nominal value.

You can synchronize the internal PWM clock with an external clock frequency. The external source must be within the minimum and maximum synchronization range programmed into the IC.

The capture range for the SYNC period is 87.5% to 112.5% of the programmed switching period. The switching frequency synchronized to the SYNC pin is limited by the programmed frequency. A frequency synchronization feature is optional. When enabled, the switching frequency can be programmed to 1, 1/2, 1/3, or 1/4 of the SYNC frequency.

To achieve high efficiency at light load, the ADP1048 can shut down one phase or PWM output under light load conditions. When the input power drops below the low power threshold, PTH, one PWM output is disabled. When the input power goes above the low power threshold plus power hysteresis, the PWM resumes operation.


A dedicated current limiting pin (ILIM) protects the IC from pulse-by-pulse overcurrent events. If the limit threshold is crossed, the PWM pulse is terminated and operation resumes at the next switching cycle unless a different action is specified for the fast OCP (overcurrent protection) response. An OCP comparator on the ILIM pin can accept positive or negative signals; the pin is referred to PGND (power ground) and has programmable level shifting current sources. These sources can be changed during normal operation to adapt to the triggered level of overcurrent protection.

OVP (overvoltage protection) uses information available on the ADC connected to the VFB pin. Information from the VFB ADC is averaged over one half the ac line frequency; therefore, the response of this OVP is relatively slow.

There is also a fast OVP mode that uses a programmable comparator on the OVP pin. The fast OVP signal is fed into a comparator with a programmable threshold to set the trip point for overvoltage.

You can connect a PTC (positive temperature coefficient) or NTC (negative temperature coefficient) thermistor to the RTD pin. If the temperature sensed at the RTD pin exceeds the programmable fault threshold, the IC sets the OTP (overtemperature protection) flag, and you can program the power supply to shut down if this occurs.

There is also open-loop protection to detect differences between the OVP and VFB pins. This protection detects a difference in voltage in excess of ~100 mV, which equates to approximately 6.6% of the full-scale range.

The ADP1048 has two digital status pins: AC_OK and PGOOD. AC_OK flag verifies the AC input is present. PGOOD flag confirms that the dc output is regulated. Designers can program the circuit to blank flags for the AC_OK and PGOOD signals.

Compensation Filters

The ADP1048 offers filter presets that set the control loop’s dynamic response and optimize operating conditions. Included are a low and high line current filters and a fast voltage compensation filter. The ADP1048 can be configured to switch automatically between the high and low line filters when the rms value of the ac line crosses a programmed threshold between the high and low lines.

There is a check for the value of the rms input voltage at each half line cycle. When the IC detects a transition between the high and low line thresholds, it waits for four full line cycles before switching to the correct filter at the zero crossing of the input line cycle. This is done to avoid spurious transitions due to a missing or distorted voltage line cycle.

During transients, a fast loop mode is enabled to allow for faster loop responses. The fast loop mode has separate settings and can be programmed to respond quickly to load transients. The user can disable the fast loop mode if not required by the application.

To ensure a smooth transition, the ADP1048 switches from the regular filter to the fast loop filter at the zero crossing of the rectified input voltage. When the output voltage returns to regulation within the programmed band, the controller switches back to the normal loop at the next zero crossing of the rectified input voltage. If the output voltage does not return to regulation within the programmed band after a fixed time of 630 ms, the control loop automatically switches back to the normal loop. In the normal compensation loop, the sampling frequency of the output voltage is the same as the ripple oscillation frequency (which is commonly 100 Hz or 120 Hz). Based on the requirements of the application, the designer can program the circuit to enable or disable the fast loop mode.

AC Line Detection

The ADP1048 is capable of detecting several parameters of the ac line input voltage and taking the appropriate programmed actions when necessary. The detection is a combination of time and voltage measurements and is implemented via the VAC pin, which detects the rectified ac input voltage. This allows early detection of ac line faults and early warning for the host system, thereby increasing reliability.

The input ac line period is measured every half period of the ac line cycle. During the first 40 ms, the ac line period is measured between two consecutive falling crossings of the programmed threshold value. The ac line period is then measured between two consecutive falling crossings and compared to the average value of the input line voltage, which is calculated during each half line period. This information is used by the control loop, as well as the power-metering block.

To operate, the controller must detect the ac line value. At startup, the controller waits for the PSON signal (hardware PSON, software PSON, or both, depending on how the part is programmed). When the PSON signal is present, the controller looks for the ac line period and value.

Soft Start

A signal on the PSON pin can enable or disable the PFC stage. After asserting the PSON signal the ADP1048 starts monitoring VAC and, if the ac line conditions are met, they initiate the soft start procedure shown in Fig. 5.

Startup is gated by the rms value of the ac line voltage measured on one half period of the ac line frequency. When VAC is above the VIN_ON value, it initiates the soft start sequence. At the same time, the inrush delay time and soft start delay time timers begin. Both of these timers can be programmed to count 0 to 7 line cycles (or 0 to 14 half line cycles in steps of 2).

After a programmed inrush delay time, the IC asserts the inrush signal (Pin 17), closing the inrush current relay. The inrush signal is set at the zero crossing of the ac voltage, if this crossing is detected. This setting allows zero voltage turn-on if a solid-state switch is used (zero voltage turn-on is not relevant with mechanical relays). After the soft start delay time, the output voltage is ramped up according to the programmed soft start time. When output voltage regulation is reached the PGOOD signal (Pin 16) is asserted.

You can program the ADP1048 IC’s soft start time to 112 ms, 168 ms, 224 ms, 280 ms, 392 ms, 504 ms, 616 ms, or 728 ms. The soft start delay time can be programmed from 0 to 7 full line cycles in increments of 1 (that is, two of the rectified half line cycles).

Inrush delay time can be programmed from 0 to 7 full line cycles in increments of 1 (two of the rectified half line cycles). If no zero crossings are detected, it uses the programmed maximum ac line period.

Line Fault Protection

Line faults occur when the ac line is not behaving correctly and include anomalies such as a missing ac line cycle (can be partial), brownout, or high distortion levels. You can program the ADP1048 to react according specific line faults.

The ADP1048 monitors and communicates critical information, including input and output voltage, input and output current, temperature, and efficiency. It also monitors and communicates OVP, UVP (undervoltage protection), OCP, OTP, and open-loop protection functions. An I2C interface reads all these values and flags and programs their thresholds. The on-chip EEPROM can store all of the settings for these thresholds.

Fault Monitoring

The controller’s fault monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out of limit for current, voltage, power, and temperature. The limits for the fault conditions are programmable. A flag indicates a fault condition; therefore, a flag is set (equal to 1, or high) when the fault or bad condition occurs.

When multiple faults occur at the same time, the state machine executes the response that has the highest priority. If two or more faults occur at the same time and all the faults have the same response priority, the fault with the smallest retry setting takes priority.

For higher efficiency, the switching frequency of the ADP1048 can be programmed according to the load power condition. The smart switching frequency feature uses two different switching frequencies for heavy load and light load conditions. When the output power is lower than the low power threshold, PTH, the PFC circuit switches at the fSL frequency. When the output power is higher than PTH plus power hysteresis, the circuit switches at the normal set frequency, fS.

The ADP1048 power factor correction controller can be programmed using an easy-to-use, graphic user interface (GUI) which allows power engineers to program the device without the use of complex code. The user can download the settings from the GUI direct to the EEPROM on-board the ADP1048. This implementation results in a robust software structure which becomes easy to control and qualify.

A demonstration of the GUI design tool for the ADP1048 can be found at http://www.engineeringtv.com/video/Vicor-Design-Tool.

Related Articles:

Getting the Most out of Power Factor Correction

Simplifying Power Factor Correction in SMPS

Choosing Between Semi-Bridgeless and Interleaved PFC Pre-Regulators

Minimize Winding Losses in High-Frequency Inductors

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