This article appeared in Microwaves & RF and has been published here with permission.
This article is part of our Design Automation Conference 2023 coverage.
Promising a faster time-to-market with better system-on-chip (SoC) economics, Arteris said its system IP offering includes network-on-chip (NoC) interconnect IP as well as SoC integration automation software for higher performance and lower power consumption.
FlexNoC 5 physically aware interconnect IP delivers up to 5X faster physical convergence, according to the company. This latest NoC IP release offers improvements over manual methods with fewer iterations, reducing costly redesigns and optimizing performance. It enables place-and-route tools to have a better starting point, shrinking interconnect area by 15% or more over legacy approaches while reducing NoC IP power in the process. It can be used with any processor technology, including Arm or RISC-V.
Arteris' Magillem Connectivity is able to speed the design of complex systems, streamlining and shortening the process by as much as 30%. It can accelerate IP deployment, too, allowing for continuous integration in a flexible, automated hardware-development flow.
Using a data model based on the IP-XACT industry standard, Magillem Connectivity enables IP packaging that handles all aspects of system integration for connectivity and configurability. The tool can increase productivity, adding predictability with progress reporting, with a portable design environment. Magillem Connectivity also delivers automated hierarchy manipulation capabilities that have built-in checks with separate RTL hierarchy and physical hierarchy, while synchronizing connectivity and memory map information with Magillem Registers.
Magillem Registers automatically builds error-free system memory maps, providing a single source of truth methodology based on the IP-XACT standard. This leads to quick and scalable automated implementation, accelerating time-to-market for hardware/software interface generation by as much as half. It translates the specification of registers into executable design code, automatically importing register descriptions from different sources and formats into IP-XACT.
Magillem Registers also automatically checks the accuracy of the information, facilitating collaboration between HW, SW, and tech doc teams using a single source of truth methodology. Supporting customizable generators with automatic generation of standard output formats, it synchronizes connectivity and memory map information with Magillem Connectivity:
The company's CSRCompiler streamlines the creation of hardware-software interfaces, and in combination with the CSRSpec language, automates the creation of a proper hardware/software interface. Providing a complete register design solution for hardware, software, verification, and documentation, the CSRCompiler system and CSRSpec language allows teams to manage their designs collaboratively from a single source specification. This ultimately helps ensure a complete, correct, and up-to-date register design ecosystem.
Read more articles from our Design Automation Conference 2023 coverage.