Power Electronics

Peak Current-Mode DC-DC Converter Stability Analysis

Peak current-mode control (PCMC) with slope compensation has advantages of automatic input line feed forward, inherent cycle-by-cycle overload protection, and current sharing capability in multi-phase converters.

Popularity and perceived advantages of current-mode control (CMC) have made it de rigueur as a loop control architecture with many power management IC manufacturers and power supply vendors. Also known as multi-loop control, an external voltage loop and a wide-bandwidth inner current loop are standard. Peak, valley, average, hysteretic, constant on-/off-time, and emulated current-mode techniques are realizable. Top of the agenda is usually peak current-mode control (PCMC) with slope compensation. Notable advantages of PCMC include automatic input line feed-forward, inherent cycle-by-cycle overload protection, and current sharing capability in multi-phase converters. Acute shortcomings are current loop noise sensitivity and switch minimum on-time limitations, particularly in high step-down ratio, non-isolated converter applications. The emulated (sample-and-hold) architecture[1,4] largely alleviates these shortcomings, however, while preserving the benefits of PCMC.

The converter in Figure 1 represents a single-phase buck topology operating in continuous conduction mode (CCM), and whose duty cycle, D, is determined by recourse to the principles of PCMC. Note that the parasitic resistances of the filter inductor and output capacitor are denoted explicitly. Other buck-derived power stage topologies - including isolated forward, full-bridge, voltage-fed push-pull - could also be inserted here, while retaining a similar loop configuration (feedback isolation excepted).

In a peak current-mode architecture, the state of the inductor current is naturally sampled by the PWM comparator. The outer voltage loop employs a type-II voltage compensation circuit and a conventional operational transconductance error amplifier (EA) is shown with its inverting input, labeled the feedback (FB) node, connected to feedback resistors Rfb1 and Rfb2. A compensated error signal appears at the EA output, labeled COMP, the outer voltage loop thus providing the reference command for the inner current loop. COMP effectively represents the programmed inductor current level. The current loop converts the inductor into a quasi-ideal voltage-controlled current source, effectively removing the inductor from the outer loop dynamics, at least at DC and low frequencies.

The current sensing location in Figure 1 is shown schematically after the inductor. The implementation could be a discrete shunt resistor, or lossless using inductor DCR current sensing[5] or measuring MOSFET on-state resistance[2]. Alternatively, a current sense transformer can be exploited, but only if the current sense location is such that the current waveform is zero for part of the switching period to allow transformer reset, e.g. in series with the high-side FET. In any event, the equivalent linear amplifying multiple is given by:

Where:

Gi = Current sense amplifier gain (if used)

Rs = Current sensor gain given by one of:

A perfect current-mode converter relies only on the dc or average value of inductor current. In practice, a peak-to-average inductor current error exists in a PCMC implementation and this error can manifest itself as a sub-harmonic oscillation of the current loop in the time domain at duty cycles above 50%. Slope compensation is the well-known technique of adding a ramp to the sensed inductor current to obviate the risk of this sub-harmonic oscillation. Figure 2 illustrates how a turn-on command is activated when the clock edge sets the PWM latch. A turn-off command is imposed when the sensed inductor current peak plus slope compensation ramp reaches the COMP level and the PWM comparator resets the latch. This is known as trailing edge modulation. Se, earmarked in Figure 2, is the external slope compensation ramp slope and Sn and Sf are the on-time and off-time slopes of the sensed current signal, respectively. D' = 1-D is the duty cycle complement.

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CMC SMALL-SIGNAL REVIEW

The analytical nexus around which a small-signal dynamic model can be derived is based either on Middlebrook and Cuk's famous state space averaging (SSA) technique or, more simply, Vorpérian's PWM switch model. An intuitive model of the small-signal current-mode system is illustrated in the block diagram format of Figure 3[1].

Modulator gain block KM is the gain from the duty cycle to the switch-node voltage. Contingent upon the load characteristic, Ro represents the small-signal AC load resistance given by:

Where:

R = DC operating point of the load.

The component Rdc in Figure 3 is the cumulative series resistance attributed to the inductor DCR, MOSFET on-state resistance, and PCB trace resistance

From Figure 3, the small-signal ac variation of the switch-node and output voltages are written as

Thus, the control-to-output transfer function is:

This describes the small-signal behavior of the modulator and power stage when the small-signal input voltage variation is zero. The expressions for impedances Zo(s) and ZL(s) can be substituted into (4) to obtain the pole/zero form of the control-to-output transfer function as:

H(s), the high-frequency extension in the control-to-output transfer function to model the modulator sampling gain, is discussed in more detail in the next section. The relevant gain coefficients can be derived as:

The dominant filter pole and capacitor ESR zero frequencies are given respectively by:

A typical control-to-output transfer function frequency response is elucidated in Figure 4. The pole and zero locations are denoted by × and o symbols, respectively.

SAMPLING GAIN

A current-mode control system is a sampled system, the sampling frequency of which is equal to the switching frequency. A traditional low-frequency averaged model can be modified to include the sampling effect in the current loop. Ridley[3] advised that the sampling action in the peak current-mode loop is an infinite order system but can be represented in the frequency range of interest by a pair of complex RHP zeros in the current feedback path, denoted using the gain block He(s) in Figure 3, where:

The closed-current feedback loop thus becomes unstable if it has enough gain leading to sub-harmonic oscillation. In the control-to-output transfer function, the sampling action is represented as a pair of complex RHP poles located at half switching frequency such that:

For any converter, the quality factor, Q, is:

with the slope compensation parameter defined as:

For single-cycle damping of an inductor current perturbation, the baseline requirement is that the slope compensation ramp should equal the inductor current down-slope[1], i.e.

Accordingly, a perturbed inductor current will return to its original value in one switching cycle and the resultant Q factor, calculated from (12), is equal to 2/π or 0.637. Even though most PCMC implementations exploit a fixed slope compensation ramp amplitude, the ideal slope compensation level is proportional to output voltage.

Note that excessive slope compensation increases mc, decreases Q, reduces the current loop gain and bandwidth. This portends additional phase lag in the voltage loop and stymies the maximum attainable crossover frequency. The system becomes inherently tilted towards voltage-mode control. Conversely, insufficient slope compensation decreases mc and increases Q, causing peaking in the current loop gain and ultimately voltage loop instability as duty cycles exceed 50%. A Q value in the range 0.5 to 1.0 is generally satisfactory.

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TRANSFER FUNCTION

A type-II compensator using an EA with transconductance, gm, is shown in Figure 5. The dominant pole of the EA open-loop gain is set by the EA output resistance, REAout, and effective bandwidth-limiting capacitance, Cbw, as follows:

The influence of any EA high frequency poles, whether parasitic or included by design, is neglected in the above expression. The compensator transfer function from output voltage to COMP, including the gain contribution from the feedback resistor divider network, is given by:

With:

And the feedback attenuation factor is:

Evaluating (17) gives an expression of the form

As ωpEA1 and ωpEA2 are well separated in frequency, the low Q approximation applies and (19) becomes

Where:

Typically, Rcomp ≪ REAout, Ccomp ≫ (Chf + Cbw) and the approximations set forth in (21) are valid. The components creating the two compensator poles and one compensator zero are circled in Figure 5.

Here, the feedback attenuation is unity and the EA has open-loop dc gain of 50dB and 5MHz single-pole gain-bandwidth characteristic. Again, the poles and zeros are denoted with × and o symbols, respectively, and a + symbol indicates the EA bandwidth. Note that the 180° phase lag related to the EA in the inverting configuration is not included in the phase plots.

Compensator pole ωpEA1 shown in Figure 5 appears at very low frequency and can be superseded by an integrator term. The equation for the compensator transfer function thus can now be simplified to:

The integrator gain term, Ac, is given by

CMC COMPENSATOR DESIGN

A frequently employed, yet corrigible, compensation strategy is to equate the control-to-output transfer function to the compensator transfer function term by term to attain a single-pole -20dB/decade roll-off of the loop response. To demonstrate, consider:

  • One compensator pole, ωpEA1, positioned to provide high gain in the low frequency range, minimizing output steady state error for better load regulation;

  • One compensator zero located to offset the dominant load pole, ωzEA = ωp. Typically, the minimum load resistance (maximum load current) condition is used;

  • One compensator pole positioned to cancel the output capacitor ESR zero, ωpEA2 = ωesr;

The loop gain is expressed as the product of the control-to-output and compensator transfer functions. Substituting (5) and (22), the loop gain is

The crossover frequency, ωc = 2πfc, where the loop gain is 0dB, is usually selected between one tenth and one fifth of the switching frequency. If ωzEA = ωp and ωpEA = ωesr, the loop gain reduces to

Assuming a well designed current loop (Q = 0.637), the sampling gain contribution is insignificant at frequencies up to the crossover frequency. This assumption precludes the case where too much slope compensating ramp is added. The magnitude of the loop gain at the dominant pole frequency is:

Using basic bode plot principles, it is apparent that

Thus derived, a straight-forward solution for the crossover frequency is

Finally, compensator component values can be calculated sequentially as

An initial value is selected for Rfb2 based on a practical minimum current level flowing in the divider chain. Note that the compensation zero frequency represents the dominant time constant in a load transient response characteristic. A large Ccomp capacitor is thus antithetical to a fast transient response settling time. Ccomp can be reduced, however, to tradeoff phase margin and settling time. A phase margin target of 50° to 60° is ideal. It is found that the compensator zero is optimally located above the load pole but below the power stage resonant frequency, ωLC ≈1/ √LCo, so that:

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Furthermore, a smaller compensation capacitance is advantageous when the transconductance EA has a low output drive current capability.

DESIGN EXAMPLE

The circuit operating conditions, key component values and control circuit parameters of a buck converter based on one channel of a LM5642X dual-channel synchronous buck

The relevant gains and power stage corner frequencies are calculated using expressions (6) through (9) as follows:

The compensation component values, assuming a desired crossover frequency of 60kHz, are found using (29) and (30) as:

Figure 6 shows a Mathcad derived loop gain and phase plot of the exemplified converter. The equivalent plots with an ideal EA are also shown. The phase margin, ϕM, is the difference between the loop phase and -180° (EA inversion phase lag notwithstanding).

SIMPLIS SIMULATION

Using a LM5642X PWM controller in a buck converter configuration (Table), a SIMPLIS switching model circuit simulation is used to substantiate the analysis. The SIMPLIS model is presented in Figure 7.

The loop gain T(s) of the system is measured by breaking the loop at the upper feedback divider resistor, injecting a variable frequency oscillator signal, and analyzing the frequency response. The element with reference designator X1 is the SIMPLIS clock edge trigger to find the circuit periodic operating point (POP) before running the ac analysis. POP analysis works on the full non-linear switching time domain model of the circuit and enables subsequent ac or transient analyses. Figure 8 illustrates the bode plot simulation.

REFERENCES

  1. R. Sheehan, National Semiconductor, ‘Current-Mode Modeling - Reference Guide’, www.national.com/analog/power/conference_paper_design_ideas

  2. National Semiconductor LM5642 High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization from the PowerWise® Family, www.national.com/pf/LM/LM5642.html

  3. R. B. Ridley, ‘A New, Continuous-Time Model for Current-Mode Control’, IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991, pp. 271-280.

  4. National Semiconductor LM3000 Dual Synchronous Emulated Current-Mode Controller from PowerWise® Family, www.national.com/pf/LM/LM3000.html.

  5. National Semiconductor LM27402 High Peerformance Buck Controller with DCR Current Sensing from PowerWise® Family, www.national.com/pf/LM/LM27402.html.

Table: LM5642X Buck Converter Parameters

Vin 24V fs 375kHz Cbw 11pF
Vo 5.0V Rdc 5mΩ Vslope 0.25V
Io 5A Resr 5mΩ Se 94mV/µs
D 0.208 Rs 20mΩ Sn 353mV/µs
L 5.6µH Gi 5.2 mc 1.266
Co 50µF gm 720µâ„¦-1 Q 0.634
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