Power Electronics
FAQs: Low Dropout (LDO) Linear Regulators

FAQs: Low Dropout (LDO) Linear Regulators

Low dropout linear regulators are useful where a low-noise power source is needed, and where the regulator must maintain regulation with small differences between the input supply voltage and output load voltage, such as battery-powered portable and wireless systems. 

What are typical applications for a low dropout (LDO) linear regulator?

LDO linear regulators are usually employed in systems that require a low-noise power source instead of a switching regulator that might upset the system. LDOs also find use in applications where the regulator must maintain regulation with small differences between the input supply voltage and output load voltage, such as battery-powered systems. Their low dropout voltage and low quiescent current make them a good fit for portable and wireless applications.

 

How much output current can an LDO provide?

LDOs with an on-chip power MOSFET or bipolar transistor typically provide outputs in the 50 mA to 1 A range. Some newer circuits can actually handle higher currents.

What is a typical LDO regulator circuit?

An LDO voltage regulator operates in the linear region with the topology shown in the Figure. As a basic voltage regulator its main components are a series pass transistor (bipolar transistor or MOSFET), differential error amplifier, and precise voltage reference.

LDO voltage regulator employs a series pass transistor (bipolar transistor or MOSFET), differential error amplifier, and precise voltage reference.
LDO voltage regulator employs a series pass transistor (bipolar transistor or MOSFET), differential error amplifier, and precise voltage reference.

One input to the differential error amplifier, set by resistors R1 and R2, monitors a percentage of the output voltage. The other error amplifier input is a stable voltage reference (VREF). If the output voltage increases relative to VREF, the differential error amplifier changes the pass-transistor's output to maintain a constant output load voltage (VOUT).  The enable EN input is used to sequence multiple LDOs and/or place the LDO input an ultra-low power dissipation state.

What characteristics affect an LDOs performance?

Key operational factors for an LDO are its dropout voltage, power supply rejection ratio (PSRR), output noise, and quiescent current..

What is dropout voltage?

Low dropout refers to the difference between the input and output voltages that allow the IC to regulate the output load voltage. That is, an LDO can regulate the output load voltage until its input and output approach each other at the dropout voltage. Ideally, the dropout voltage should be as low as possible to minimize power dissipation and maximize efficiency. Typically, dropout is considered to be reached when the output voltage has dropped to 100mV below its nominal value. The load current and pass transistor temperature affect the dropout voltage.

What is PSRR?

Power-supply rejection ratio (PSRR) affects the LDO's ability to prevent output voltage fluctuations caused by variations in input voltage. PSRR is usually specified at a specific frequency, for example 60dB rejection at 120 Hz. Low-ESR output capacitors and added reference voltage bypass capacitors improve the PSRR performance. Battery-based systems should employ LDOs that maintain high PSRR at low battery voltages.

What affects an LDO’s output noise?

An LDO's internal voltage reference is a potential noise source, usually specified as microvolts rms over a specific bandwidth, such as 30 µV rms from 1 to 100 kHz. This low-level noise causes fewer problems than the switching transients and harmonics from a switchmode converter. In the Figure, the LDO has a (voltage-reference) bypass pin to filter reference voltage noise with a capacitor to ground. Adding the datasheet-specified input, output, and bypass capacitors usually results in a non-problematic noise level.

What is quiescent current ?

Another important characteristics is the quiescent, or ground current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input to output voltage limits the efficiency of LDO’s and should be minimized.

How does the output capacitor affect LDO performance?

Controlling the LDO’s frequency compensation loop to include the load capacitor reduces sensitivity to the capacitor’s ESR (equivalent series resistance), which allows a stable LDO with good quality capacitors of any type. In addition, output capacitor placement should be as close as possible to the output.

What circuit features can enhance LDO performance?

·      An enable input that allows external control of LDO turn-on and turn-off, which allow the sequencing of supplies in multi-rail systems.

·      Soft-start that limits inrush current and controls output voltage rise time during power-up.

·      A sleep state that minimizes power, particularly in battery-based systems.

·      A bypass pin that allows an external capacitor to reduce reference voltage noise.

·      An error output that indicates if the output is going out of regulation. Also known as a voltage good or power good output.

·      Thermal shutdown that turns the LDO off if its temperature exceeds the specified amount.

·      Overcurrent protection (OCP) that limits the LDO’s output current and power dissipation.

What factors determine the optimum LDO for a specific application?

Among the considerations are the type and range of the applied input voltage, required output voltage, maximum load current, minimum dropout voltage, quiescent current, power dissipation, and shutdown current.

TAGS: Design FAQs
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