Power Electronics
Phase Shifting Optimizes Multistage Buck Converters

Phase Shifting Optimizes Multistage Buck Converters

Phase shifting further enhances the performance of synchronous buck converters as load currents extend into the 150-A range.

In a power-supply topology for a computer system with a 12-V input and a 1-V, 20-A output, currents are high enough that duplicate power stages can be used to reduce stress and spread the thermal loading. Two multiphase converter approaches are possible: one with phase shifting and one without. The supply without phase shifting could be viewed as multiple controllers with a load-share bus. The supply with phase shifting can use the TPS40140 to control the phase of each power stage.[1]

Typical computer power-supply requirements are presented in Table 1. This supply is subject to substantial surge currents from the system, so transient response is important to maintain small changes in the output voltage. Since this unit is to be used in the computing industry, the two main concerns are the size and cost of the power supply.

The converter with phase shifting significantly reduces both input and output ripple current. Reducing the ripple current will allow for less input and output capacitance, reduce power dissipation and improve efficiency. Both designs use a 6-phase approach to achieve the 120-A design goal. Each power stage is the same for both approaches and optimized to handle 20 A. Fig. 1 shows a comparison of the two approaches. The design on the left shows a configuration that has no phase shift, while the design on the right shows 60 degrees of phase shift between each phase.

Input Ripple Cancellation

The input and output capacitors of a typical notebook or desktop PC contribute a significant amount to the cost of the power supply. Also, the input and output bulk capacitors occupy a large space, which reduces the power density.

In the phase-shifted interleaved supply, the parallel converters are switched at specific phase angles. The angles are evenly distributed so that a maximum ripple current cancellation can be achieved. In the following equations, it is assumed that the input dc current is mainly provided by the input dc source and the ac current is provided by the input capacitors. Also, the parasitic components and the output ripple current are ignored. Eq. 1 shows the normalized input root-mean-square (rms) current, which is defined as a fraction of the output load current:

where k(NPH, D) = floor(NPH × D), the floor function returns the greatest integer less than or equal to the input value, NPH is the number of active phases and D is the duty cycle.[2]

Parameter Specification
Input voltage 10.8 V to 13.2 V
Output voltage 1 V
Output current 120 A
Output-voltage ripple < 10 mVP-P
Input-voltage ripple < 100 mVP-P
Switching frequency 230 kHz per phase
Table 1. Computer system power-supply electrical specifications.

Fig. 2 shows the relationship between the normalized input rms current and the duty cycle. The input ripple current cancellation is related to the number of phases and duty cycle. Greater ripple reduction is generally achieved with additional phases. Also, minimum input ripple is found at specific duty cycles related to the number of phases used.

According to the parameters defined by Eq. 1, the input ripple current cancellation factor for the interleaved supply is shown in Eq. 2 and calculated to be 0.084:

Without equal phase shifting, all the high-side MOSFETs could be switched on at the same time. The ac current is sourced by the input capacitors simultaneously and with a very high current slew rate. The rms input ripple current can be calculated for the noninterleaved case as shown in Eq. 3:

This is almost four times the input ripple current of the interleaved approach, which is normalized for various channel counts in Fig. 2. Large ripple current will cause very high power dissipation in the input capacitors due to the capacitor equivalent series resistance (ESR). The capacitor lifetime also will be reduced. The number of capacitors required for the noninterleaved approach will be four times that of the interleaved to maintain the same input voltage ripple.

In addition to the reduction of the input ac rms current, the peak-to-peak current is also reduced due to interleaving. The switching current in the input capacitor is typically a large source of electromagnetic interference (EMI) noise. With the reduced switching current amplitude, the current slew rate is reduced while providing the ac current to the high-side MOSFET. Hence, the EMI noise is reduced. With interleaving, the input ripple frequency will be six times higher than that of single-phase operation. The higher frequency makes the EMI filter smaller and less costly.

Output Ripple Cancellation

Similar to the input ripple cancellation, the output ripple current is also reduced because of interleaving. Reducing the output ripple current allows fewer output capacitors to maintain the same amount of output voltage ripple. Eq. 4 shows the peak-to-peak output ripple current cancellation factor:

where D is the duty cycle for a single phase and NPH is the number of active phases.

The relationship between the peak-to-peak output ripple cancellation factor, duty cycle and phase number is shown in Fig. 3. For a 6-phase 12-V to 1-V converter, the ripple cancellation factor is calculated to be 0.5. Eq. 5 shows the peak-to-peak ripple current for the interleaved case:

Without equal phase shifting, the peak-to-peak output ripple current is considerably higher. Eq. 6 shows the calculation of the peak-to-peak output ripple current for the noninterleaved approach:

This is more than 13 times the peak-to-peak ripple current of the interleaved case. Therefore, a nonphase-shifted approach would require 13 times as much output capacitance to maintain the same output voltage ripple, which adds to the area and cost of the power supply.

Simulation and Experimental Results

The two designs compared input and output ripple voltage and the number of components required to meet the design specifications. In all situations, the interleaved approach was found to have better performance than the noninterleaved approach. The simulation results comparing the two approaches are shown in Table 2.

Parameter Interleaved Noninterleaved
RMS input ripple 10.38 A 37.2 A
Peak-to-peak input ripple 24.3 A 145 A
RMS output ripple 0.75 A 10.1 A
Peak-to-peak output ripple 2.65 A 34.7 A
Ripple frequency 1.38 MHz 230 kHz
Table 2. Ripple current simulation results.

Because the ripple current is much higher for the noninterleaved case, many more capacitors are required to meet the specifications. The chosen output capacitors for this application are 4-V, 470-µF, 10-mΩ Specialty Polymer (SP) capacitors from Sanyo. The input capacitors are a mixture of 16-V, 22-µF ceramic capacitors and 16-V, 180-µF OS-CON capacitors. Table 3 shows the voltage ripple results and the required number of capacitors for each case.

Parameter Interleaved Noninterleaved
Output voltage ripple 4.8 mV 9.8 mV
470-µF output capacitors 1 per phase 6 per phase
Input voltage ripple 41 mV 99 mV
180-µF OS-CON input capacitors 2 per phase
22-µF ceramic input capacitors 1 per phase 4 per phase
Table 3. Ripple voltage and capacitor requirements.

The results show that the interleaved approach provides a significant advantage in terms of number of capacitors for both the input and the output. In addition to the component savings, the input and output voltage ripple is improved.

The experimental results of the interleaved solution were checked to ensure that the simulations are accurate. The measured input voltage ripple is ~60 mV and the output voltage ripple is ~6 mV. Both of these values are close to the simulated results. Fig. 4 shows the input and output voltage ripple of the interleaved supply. In reality, the ripple current cancellation effect will be limited to some extent based on the parasitic component values.

Phase Stackability

In high current systems, there are often lower current states and sleep states. During these states, it is usually desirable to reduce the power consumption. One way to achieve this is to shut down unneeded phases. Conversely, there are times in which more power is needed and another phase could be added. Another useful feature is the ability to build modular systems, so that more phases can easily be added or removed if the system specifications change.

The TPS40140 from Texas Instruments is a dedicated power-supply controller for low-voltage and high-output current applications. It has a very wide input-voltage range (2 V to 40 V) and a wide output range (0.7 V to 5.8 V) that fits most point-of-load (POL) applications. Each TPS40140 can be configured for a stackable multiphase synchronous buck supply. A stackable supply is one in which more phases can easily be added to increase the current capability of the power supply.

In a multiphase configuration, one TPS40140 is configured as a master, while the others operate as slaves. The same IC is used for both the master and the slaves. A digital clock is generated in the master and distributed to the other slave ICs. The slaves detect the clock signal and then synchronize to the appropriate phase angles.

The TPS40140 can provide fully interleaved operations for 2, 3, 4, 6, 8, 12 and 16 phases. For this application with the 120-A output load, three TPS40140 ICs are used to form a 6-phase converter. Programming the devices for this configuration is accomplished through a resistor stack as shown in Fig. 5. The value for each resistor in the stack is 39 Ωk. The phase select pin of the master supplies 20 µA to the top of the stack, and each slave senses the voltage across its own phase select pin. The dual outputs of each TPS40140, master or slave, are 180 degrees out of phase.

The inductor dc resistance (DCR) method is the preferred method for sampling the output current for the TPS40140. This is a lossless approach, as opposed to using a discrete current sense resistor, which occupies board area and impacts efficiency as well. The inductor DCR implementation is shown in Fig. 6. The accuracy of this technique depends on the ability to match the time constant of the R1-C1 circuit with the L1 DCR circuit.

Fully interleaved multiphase synchronous buck solutions offer significant advantages over noninterleaved solutions. The interleaved solution reduces the input and output current ripple and, thus, the number of necessary capacitors. It also reduces the power-supply area and total cost while improving performance and efficiency. Table 4 summarizes the advantages of the interleaved solution.

Parameter Interleaved Noninterleaved
Output capacitors 1 SP per phase 6 SP per phase
Input capacitors 1 ceramic per phase 4 ceramic plus 2 OS-CON per phase
Efficiency at 120 A 88.70% 85% (estimated)
Size Baseline 25%
Cost Baseline 25%
Table 4. Interleaved design shows advantages over noninterleaved.


  1. TPS40140 datasheet, Texas Instruments, July 2006.

  2. Using the TPS40090EVM-002 User's Guide, SLUU195, Texas Instruments, June 2004.

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